Possible Origins and Some Methods to Minimize LER

Padmanaban, Murirathna; Rentkiewicz, David; Hong, Chisun; Lee, Dongkwa; Rahman, Dalil; Sakamuri, Raj; Dammel, Ralph R.

doi:10.2494/photopolymer.18.451

Cited by 10 publications

(4 citation statements)

References 13 publications

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“…[11][12][13] This is usually considered as a Poisson distribution of beam electrons. [11][12][13] This is usually considered as a Poisson distribution of beam electrons.…”

Section: Shot Noisementioning

confidence: 99%

Study on line edge roughness for electron beam acceleration voltages from 50to5kV

Río

Constancias

Saied

et al. 2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…[11][12][13] This is usually considered as a Poisson distribution of beam electrons. [11][12][13] This is usually considered as a Poisson distribution of beam electrons.…”

Section: Shot Noisementioning

confidence: 99%

Study on line edge roughness for electron beam acceleration voltages from 50to5kV

Río

Constancias

Saied

et al. 2009

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…The semiconductor industry has specified the requirements for photoresists and lithographic exposure tools at future technology nodes in the International Technology Roadmap for Semiconductors (ITRS) . Particularly troublesome has been the inability of conventional photoresist materials to meet the critical dimension control (CD referring to the dimension of the smallest patterned feature of importance, e.g ., the transistor gate length in MPUs) and line edge roughness (LER) requirements, both of which should have been at sub 3 nm levels by the year 2009. , The frequency of the line edge roughness, in addition to the magnitude of the LER, is an important consideration for the devices to be fabricated and affects the operation of transistors, − interconnect wire resistances, , and dopant concentration profiles. For example, small wavelength roughness influences the operation of individual transistors (local variations in gate length affect the threshold voltage and current leakage, and thus overall power consumption), while large wavelength roughness affects the operation of transistor groups (variations in transistor speeds can cause integrated circuit timing issues). ,, …”

Section: Introductionmentioning

confidence: 99%

Remediation of Line Edge Roughness in Chemical Nanopatterns by the Directed Assembly of Overlying Block Copolymer Films

Stoykovich

Daoulas²,

Müller³

et al. 2010

Macromolecules

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Block copolymer structures have been directed to assemble on chemically patterned surfaces with the domain interfaces oriented perpendicular to the substrate. Such methods have been pursued for lithographic applications to achieve long-range order in the assembled structures and, potentially more important, provide nanometer-level control over the interfaces between structures. The chemically striped surfaces used for the directed assembly of lamellae are patterned by top-down lithographic techniques and thus often have rough edges between the regions of different chemistry. Here we quantitatively characterize, using experiments and molecular-level simulations, the propagation of line edge roughness from the chemically patterned surfaces into the interfaces between domains of block copolymer lamellae as a function of the wavelength, amplitude, and geometry of the roughness. Two geometries of surface pattern roughness are considered with oscillatory neighboring interfaces that are either in-phase or out-of-phase. Block copolymer lamellae of poly(styrene-block-methyl methacrylate) effectively self-corrected surface patterns with small wavelength in-phase and out-of-phase roughness such that little or no memory of the substrate pattern roughness could be observed at the top surface of a 40 nm thin film. Larger wavelength in-phase roughness, and to a lesser extent larger wavelength out-of-phase roughness, propagated farther from the surface pattern such that the domain interfaces between block copolymer lamellae maintained the roughness throughout the film. These self-healing capabilities of block copolymers will be essential for lithographic applications with tight tolerances on line edge roughness and line width control, e.g., in patterning transistor gates.

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“…Therefore studies of LER/LWR with these resolution enhancement techniques are important for future process design. Previously we discussed the origins of LER from material side, and reported influence of hard bake and RELACS™ on LER [1] and structure relationship of amine quenchers with LER [2]. In this paper, we report the influence of various process factors on LER/LWR and the mechanism of line roughness are discussed along with aerial image contrast, absorbance of resists and pattern profiles.…”

Section: Introductionmentioning

confidence: 94%

Some non-resist component contributions to LER and LWR in 193-nm lithography

et al. 2007

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Improvement of line edge roughness (LER) and line width roughness (LWR) is required for integration of semiconductor devices. This paper describes various process factors affecting LER/LWR of 193 nm resists such as mask layout (bright field/dark field), pitches, optical settings, substrates, film thickness, baking temperature and development condition. The origins of line roughness are discussed in view of aerial image contrast, transmittance of resists and pattern profiles. Bright field mask exhibited lower LER/LWR values than dark field mask, LER/LWR deteriorated as larger pitches and illumination condition affected roughness and these results are explained using normalized image log-slope (NILS). BARC dependence of line roughness is explained by pattern profile difference due to interactions between resist and BARC and in some cases BARC reflectivity. Contributions of film thickness, SB & PEB temperature and development condition to line roughness are also reported.

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Possible Origins and Some Methods to Minimize LER

Cited by 10 publications

References 13 publications

Study on line edge roughness for electron beam acceleration voltages from 50to5kV

Study on line edge roughness for electron beam acceleration voltages from 50to5kV

Remediation of Line Edge Roughness in Chemical Nanopatterns by the Directed Assembly of Overlying Block Copolymer Films

Some non-resist component contributions to LER and LWR in 193-nm lithography

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