Possible nanoelectronic implementation of neuromorphic networks

Türel, Özgür; Muckra, Ibrahim; Likharev, K. K.

doi:10.1109/ijcnn.2003.1223373

Cited by 9 publications

(4 citation statements)

References 8 publications

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“…In this way, each of two four-switch synapses connecting the cell pair is exposed to training only once and, as described in the end of the CROSSNETS section, probabilities of connection of its synapses are saturated to provide virtually deterministic weights This is the so-called "clipped Hebb rule" that is known to work very well for fully connected Hopfield networks. 55,56 Our estimates 35 show that for a CrossNet trained by this method, P max should scale as M; this is as much as could be expected from the wellknown theory of randomly diluted networks. 55,56 (The locality of CrossNets is to some extent similar to dilution.…”

Section: Hopfield-mode Trainingsupporting

confidence: 67%

“…We have used this property to demonstrate 34,35 successful training of InBar as a Hopfield (we use this commonly accepted name despite the considerable controversy concerning the authorship of this concept 61 ) network. 34 During this demonstration, we self-imposed all the restrictions anticipated for the future hardware CrossNet implementations.…”

Section: Hopfield-mode Trainingmentioning

confidence: 99%

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CrossNets: High‐Performance Neuromorphic Architectures for CMOL Circuits

Likharev

Mayr

Muckra

et al. 2003

Annals of the New York Academy of Sciences

101

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The exponential, Moore's Law, progress of electronics may be continued beyond the 10-nm frontier if the currently dominant CMOS technology is replaced by hybrid CMOL circuits combining a silicon MOSFET stack and a few layers of parallel nanowires connected by self-assembled molecular electronic devices. Such hybrids promise unparalleled performance for advanced information processing, but require special architectures to compensate for specific features of the molecular devices, including low voltage gain and possible high fraction of faulty components. Neuromorphic networks with their defect tolerance seem the most natural way to address these problems. Such circuits may be trained to perform advanced information processing including (at least) effective pattern recognition and classification. We are developing a family of distributed crossbar network (CrossNet) architectures that permit the combination of high connectivity neuromorphic circuits with high component density. Preliminary estimates show that this approach may eventually allow us to place a cortex-scale circuit with about 10(10) neurons and about 10(14) synapses on an approximately 10 x 10 cm(2) silicon wafer. Such systems may provide an average cell-to-cell latency of about 20 nsec and, thus, perform information processing and system training (possibly including self-evolution after initial training) at a speed that is approximately six orders of magnitude higher than in its biological prototype and at acceptable power dissipation.

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Section: Hopfield-mode Trainingsupporting

confidence: 67%

Section: Hopfield-mode Trainingmentioning

confidence: 99%

CrossNets: High‐Performance Neuromorphic Architectures for CMOL Circuits

Likharev

Mayr

Muckra

et al. 2003

Annals of the New York Academy of Sciences

101

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“…The grid-like connectivity of the brain can be easily translated into a 2D or layered 3D crossbar array architecture with synaptic devices, bringing it one step closer to reach brain-level connectivity and synaptic density. Hybrid CMOS/nanoelectronic device networks or crossnets have been proposed to build neuromorphic systems [124][125][126][127][128]. These networks may be utilized to perform cognitive tasks which were originally implemented in software using neural network algorithms.…”

Section: Targeted Computing Applications With Synaptic Devicesmentioning

confidence: 99%

Synaptic electronics: materials, devices and applications

2013

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In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing. Performance metrics desirable for large-scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented.

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“…Since the capacity of such memory is very weakly affected by synaptic weight discreteness, a CrossNet with just one latching switch per synapse may operate very well in this mode; its main difference from the generic Hopfield net is the quasi-local (rather than global) connectivity M, limiting its capacity to ∼0.45 M at 99% restoration fidelity. 53 Figure 12 shows an example of such an operation; the final image is completely error free. However, the most remarkable feature of the pattern restoration is its speed (∼ 5 RC), taking into account that in realistic CrossNets the RC time constant may be below 1 s. (See Section 3 above.)…”

Section: Hopfield Network: Pattern Recognitionmentioning

confidence: 99%

CrossNets: Neuromorphic Hybrid CMOS/Nanoelectronic Networks

Likharev¹

2011

sci adv mat

100

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Hybrid CMOS/nanoelectronic circuits, combining CMOS chips with simple nanoelectronic crossbar add-ons, may extend the exponential Moore-Law progress of microelectronics beyond the 10-nm frontier. This paper reviews the development of neuromorphic networks ("CrossNets") based on this prospective technology. In these networks, the neural cell bodies ("somas") are implemented in the CMOS subsystem, crossbar nanowires are used as axons and dendrites, while two-terminal crosspoint devices are used as elementary synapses. Extensive analysis and simulations have shown that such networks may perform virtually all information processing tasks demonstrated with software-implemented neural networks, with much higher performance. Estimates show that CrossNets may eventually overcome bio-cortical circuits in density, at comparable connectivity, while operating 4 to 6 orders of magnitude faster, at manageable power dissipation.

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Possible nanoelectronic implementation of neuromorphic networks

Cited by 9 publications

References 8 publications

CrossNets: High‐Performance Neuromorphic Architectures for CMOL Circuits

CrossNets: High‐Performance Neuromorphic Architectures for CMOL Circuits

Synaptic electronics: materials, devices and applications

CrossNets: Neuromorphic Hybrid CMOS/Nanoelectronic Networks

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