path(s) with the smallest thermal resistance. In the case of packaged semiconductor devices, the dissipated energy is mainly conducted through the semiconductor die towards the backside of the die, then through several TIM (thermal interface material) layers to the passive or active cooling device (e.g.: heat sinks, heat-pipes, etc.). In order to ensure the lowest thermal resistance path the number of thermal interfaces (material transitions, mating assembly surfaces) has to be minimized. In System-in-Package (SiP) or System-on-Package (SoP) (Tummala 2007) structures the different dies are stacked on each other forming a real 3D structure. Between the dies high resistivity layers (made of some kind of glass) are formed to ensure electrical insulation. These layers also have high thermal resistivity (not to mention the thermal interfaces formed at the sides of these interposer layers), therefore the temperature elevation is higher as if the whole 3D structure was made of silicon.One way to decrease the overall thermal resistance of such a system is to bring the cooling structures closer to the dissipation sources (from now on simply referred to as junction). The thermally optimal solution is to integrate the cooling solutions into the 3D stack. Such integrated cooling solutions include integrated micro-refrigerators structures attached close to the hot-spot locations. In these applications high heat-fluxes (up to a few 100 W/cm 2 ) can be achieved with localized cooling (Jeffrey 2006). Papers Tang et al. (2010); Sabry (2011) present the method and the results of forming a microscale channel structure with circulating fluid inside. Other papers, Prechtl and Kurtz (2004) and Vladimirova (2011) describe microscale channel structure inside the die itself.Though these papers present promising new integrated cooling techniques but they do not mention how the physical realization is optimized to achieve the best possible heat transfer and they do not address how the design of these Abstract As microscale cooling structures are integral parts of modern chip level cooling concepts, the understanding the behaviour of different assemblies is desirable. This way novel co-design concepts can be created where the conventional IC design steps are extended with thermal design capabilities resulting in a SiP/SoP design flow. The first step in this process is to create a general formula which describes the heat transfer mechanism and can be implemented in IC CAD environments as a compact model. This paper presents an analytical study of an integrated microscale channel based cooling structure with the above motivation in mind. A closed analytical formula is given to calculate the partial thermal resistance corresponding to the heat transfer represented by the coolant which can be used in electro-thermal co-simulation. The analyses based on numerical CFD simulations and thermal transient characterizations of a realized structure are also discussed and the results are compared against the analytical ones.