Positive and negative tone double patterning lithography for 50nm flash memory

Abstract

Double Patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.

Design-overlay interactions in metal double patterning

“…In Equations (6,7,8), b, R x , and M x are the same as in Equations ( 3,4), ρ is the wire resistivity, and H is the height of inter-level metal insulator.…”

“…Using Equation (12) and ∆C 2l and ∆C 3l (average variation) values for the case of estimated overlay components in Table 3, we plot in Figure 5 ∆C avg as a function of congestion for the case of positive-tone process only since it is more favorable for lithography than negative-tone process [3,4]. This plot show that ∆C avg is at most 3.4% (for G = 72%) and can be as low as 2.5% for highly congested layouts (90% and more).…”

“…In Figure 6, average and worst case electrical variation and CD tolerances are plotted for positive-tone DPL, the most favorable process [3,4], in 72% congestion (congestion leading to worst ∆C). Overlay requirement determined by electrical variation tolerance is significantly smaller than overlay requirement determined by same CD variation tolerance; e.g.…”

“…DPL can be implemented in a positive-tone process, which prints lines, or negative-tone process, which prints spaces [4,6]. If positive-tone process is implemented for BEOL, interconnect spacing (s), between the two patterns is affected leading to the change of interconnect line-to-line capacitance (C LL ).…”

A matching based decomposer for double patterning lithography

“…In order to increase the minimum pitch for each lithography exposure, DPL requires a pair of patterns assigned onto different masks if the minimum distance between the pair is less than a DPL threshold [1] [2] [3] [4]. Commonly, the threshold is set to be twice the minimum feature size of the desired process.…”