Porting SLOTH system to FreeRTOS running on ARM Cortex-M3

Pinto, Sandro; Pereira, Jorge; Oliveira, Daniel; Alves, Filipe; Qaralleh, Esam A. Al; Ekpanyapong, Mongkol; Cabral, Jorge; Tavares, Adriano

doi:10.1109/isie.2014.6864903

Cited by 4 publications

(3 citation statements)

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“…For example, synchronization mechanisms such as mutual exclusion (mutex), can easily be implemented exploiting the GIC. For local resources (resources shared between the same processor) the Priority Ceiling Protocol based on the temporary raise of tasks' priority will be implemented [8]. For global resources (resources shared between different processors), we will investigate the applicability of the Multiprocessor Priority Ceiling Protocol [12].…”

Section: Preliminary Resultsmentioning

confidence: 99%

“…However, the main drawback of having tasks run as pure interrupts is the run-to-completion nature of the hardware interrupt handlers. To overcome this limitation and extend interrupts to behave also as threads, a suspending feature was implemented by modelling tasks as consisting of three segments: prologue, body and epilogue [8]:…”

Section: B Threads As Interrupts As Threadsmentioning

confidence: 99%

“…This division into thread priorities and interrupt priorities, with the latter having a higher privilege of execution, is critical on embedded real-time systems, originating a well-identified problem known as rate-monotonic priority inversion [4]. Kleyman and Eykholt have proposed the first solution [5] many years ago, and since then many other approaches have been proposed to tackle this problem [6], [7], [8], [9]. Multicore OSes, for instance, still face another problem.…”

Section: Introductionmentioning

confidence: 99%

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HcM-FreeRTOS: Hardware-centric FreeRTOS for ARM multicore

Qaralleh¹,

Lima

Gomes

et al. 2015

2015 IEEE 20th Conference on Emerging Technologies &Amp; Factory Automation (ETFA)

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Migration to multicore is inevitable. To harness the potential of this technology, embedded system designers need to have available operating systems (OSes) with built-in capabilities for multicore hardware. When designed to meet realtime requirements, multicore SMP (Symmetric Multiprocessing) OSes not only face the inherent problem of concurrent access to shared kernel resources, but still suffer from a bifid priority space, dictated by the co-existence of threads and interrupts.This work in progress paper presents the offloading of the FreeRTOS kernel components to a commercial-off-the-shelf (COTS) multicore hardware. The ARM Generic Interrupt Controller (GIC) is exploited to implement a multicore hardwarecentric version of the FreeRTOS that not only solves the priority inversion problem, but also removes the need of internal software synchronization points. Promising preliminary results on performance and determinism are presented, and the research roadmap is discussed.

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Section: Preliminary Resultsmentioning

confidence: 99%

Section: B Threads As Interrupts As Threadsmentioning

confidence: 99%