Port Contention for Fun and Profit

Abstract

Simultaneous Multithreading (SMT) architectures are attractive targets for side-channel enabled attackers, with their inherently broader attack surface that exposes more per physical core microarchitecture components than cross-core attacks. In this work, we explore SMT execution engine sharing as a side-channel leakage source. We target ports to stacks of execution units to create a high-resolution timing side-channel due to port contention, inherently stealthy since it does not depend on the memory subsystem like other cache or TLB based attacks. Implementing our channel on Intel Skylake and Kaby Lake architectures featuring Hyper-Threading, we mount an end-to-end attack that recovers a P-384 private key from an OpenSSL-powered TLS server using a small number of repeated TLS handshake attempts. Furthermore, we show that traces targeting shared libraries, static builds, and SGX enclaves are essentially identical, hence our channel has wide target application.

Data Oblivious ISA Extensions for Side Channel-Resistant and High Performance Computing

“…As a result, practitioners use slower codes to improve security-e.g., S-box or bitslice AES [36] and montgomery ladder exponentiation for RSA. 10 Our OISA provides a basis for running high-performance cryptography securely. To demonstrate the benefit, we compare the performance of T-table AES [35] (high performance, low security) vs. bitslice AES [36] (low performance, high security).…”

“…These attacks exploit how victim and adversarial programs share hardware/virtual resources on shared remote servers (e.g., an amazon EC2 cloud). Simply by co-locating to the same platform, researchers have shown how attackers can learn victim program secrets through the victim's virtual memory accesses [2], [3], hardware memory accesses [4], [5], branch predictor usage [6], [7], arithmetic pipeline usage [8], [9], [10], speculative execution [11], [12] and more. Given the many avenues to launch an attack, it is paramount for researchers to explore holistic and efficient defensive strategies.…”

ABSynthe: Automatic Blackbox Side-channel Synthesis on Commodity Microarchitectures

“…Interestingly, during our analysis we also found new sources of leakage, including some that we cannot easily associate with a single component. By focusing exclusively on contention-based side channels, ABSynthe can treat the target CPU microarchitecture and its components as black boxes, while synthesizing side channels that are stealthy [10,11], that are easy to regenerate across different architectures, and that may even combine multiple microarchitectural components to boost the signal and outperform state-of-the-art side-channel attacks.…”

“…While attacks on CPU caches are the most common, attackers may equally target other microarchitectural components, including cache directories [6], TLBs [7], and branch predictors [9]. Some recent efforts, such as PortSmash [10] and SMoTherSpectre [11], show that one can also leak secret information by crafting contentionbased attacks that exploit contention on execution ports. The high-level strategy in contention-based attacks is to replace the active evictions of prior efforts with passive monitoring, which also vastly improves the stealthiness of the attack [10].…”

“…Some recent efforts, such as PortSmash [10] and SMoTherSpectre [11], show that one can also leak secret information by crafting contentionbased attacks that exploit contention on execution ports. The high-level strategy in contention-based attacks is to replace the active evictions of prior efforts with passive monitoring, which also vastly improves the stealthiness of the attack [10]. However, these efforts still rely on exploitation primitives specific to a particular microarchitectural component, in particular execution ports.…”