Porous silicon as a substrate for the integration of high performance on-chip antennas

Performance-Issues-Mitigation-Techniques for On-Chip-Antennas – Recent Developments in RF, MM-Wave, and Thz Bands With Future Directions

“…Designed in 22 nm digital CMOS technology, the 26.6 GHz -36 GHz AoC improves its gain by 9.8 dBi and radiation efficiency by 37.3 % with the use of this method. (f) The use of low permittivity locally formed porous Si substrate: In [59], the authors have utilized a low permittivity locally formed porous Si substrate, which is also compatible with the standard low-resistivity Si substrate by an electrochemical etching process.…”

“…Third, the lens itself is also costly and often needs special mounting mechanisms [56]. DRA is a another practiced AoC gain enhancement technique [18], [59]. In order to increase the equivalent dielectric, a DRA made up of a low-loss dielectric material is placed above the Si substrate with an appropriate feeding structure with the help of an epoxy glue material, as shown in Figure 8.…”

“…In order to increase the equivalent dielectric, a DRA made up of a low-loss dielectric material is placed above the Si substrate with an appropriate feeding structure with the help of an epoxy glue material, as shown in Figure 8. integration is incompatible with modern CMOS processes [59]. Therefore, this incompatibility increases fabrication complexity significantly and develops mechanical instability issues.…”

“…However, SOI CMOS is costly than bulk CMOS. In addition, SOI CMOS does not mitigate substrate surface waves generation [59], which is a key factor for the AoC performance degradation, especially at MM-Wave. Another popular technology, which is being utilized for AoC performance enhancement is Si substrate Glass Integrated Passive Device (GIPD), whose glass substrate offers high resistivity silicon substrate (loss tangent = 0.0005, ε r =11.9, ρ > 3 kΩ-cm) and low-cost [64].…”