Polyhedral parallelization of binary code

Pradelle, Benoit; Ketterlin, Alain; Clauss, Philippe

doi:10.1145/2086696.2086718

Cited by 18 publications

(14 citation statements)

References 24 publications

(29 reference statements)

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“…Static Automatic Parallelization of Binaries: Kotha et al (2010) and Pradelle et al (2012) are the only two static methods we are aware of that have done automatic parallelization in a binary rewriter. Both these methods present results on small kernels that are a part of the polybench benchmark suite.…”

Section: Related Workmentioning

confidence: 99%

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Affine Parallelization of Loops with Run-Time Dependent Bounds from Binaries

Kotha

Anand

Creech

et al. 2014

Programming Languages and Systems

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An automatic parallelizer is a tool that converts serial code to parallel code. This is an important tool because most hardware today is parallel and manually rewriting the vast repository of serial code is tedious and error prone. We build an automatic parallelizer for binary code, i.e. a tool which converts a serial binary to a parallel binary. It is important because: (i) most serial legacy code has no source code available; (ii) it is compatible with all compilers and languages. In the past binary automatic parallelization techniques have been developed and researchers have presented results on small kernels from polybench. These techniques are a good start; however they are far from parallelizing larger codes from the SPEC2006 and OMP2001 benchmark suites which are representative of real world codes. The main limitation of past techniques is the assumption that loop bounds are statically known to calculate loop dependencies. However, in larger codes loop bounds are only known at run-time; hence loop dependencies calculated statically are overly conservative making binary parallelization ineffective. In this paper we present a novel algorithm that enhancing past techniques significantly by guessing the most likely loop bounds using only the memory expressions present in that loop. It then inserts run-time checks to see if these guesses were indeed correct and if correct executes the parallel version of the loop, else the serial version executes. These techniques are applied to the large affine benchmarks in SPEC2006 and OMP2001 and unlike previous methods the speedups from binary are as good as from source. We also present results on the number of loops parallelized directly from a binary with and without this algorithm. Among the 8 affine benchmarks among these suites, the best existing binary parallelization method achieves an average speedup of 1.74X, whereas our method achieves a speedup of 3.38X. This is close to the speedup from source code of 3.15X.

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Section: Related Workmentioning

confidence: 99%

“…In the past a few attempts have been made to parallelize affine codes directly from binaries Kotha et al (2010); Pradelle et al (2012). Though these papers present good foundational ideas and results on polybench kernels, they are only a start to parallelizing large real world affine codes.…”

Section: Introductionmentioning

confidence: 99%

Affine Parallelization of Loops with Run-Time Dependent Bounds from Binaries

Kotha

Anand

Creech

et al. 2014

Programming Languages and Systems

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“…No attempt was made to raise the level of abstraction, e.g. to reconstruct polyhedral loop representations [19]. A higher level of abstraction would almost certainly create a larger scope for the discovery of parallelism in loops, but the costs would be prohibitive for an on-line method like DBP.…”

Section: Limitationsmentioning

confidence: 99%

“…The modified binaries are executed on a CMP with hardware speculation support implementing a complex register communication scheme based on synchronizing scoreboards. Pradelle et al [19] rely entirely on off-line preprocessing of binaries to extract parallel loops using a polyhedral model. Our study differs in that it does not rely on a static preprocessing stage which would be limited in its ability to extract control and data flow information.…”

Section: Related Workmentioning

confidence: 99%

Limits of region-based dynamic binary parallelization

Koch

Franke

2013

SIGPLAN Not.

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Efficiently executing sequential legacy binaries on chip multiprocessors (CMPs) composed of many, small cores is one of today's most pressing problems. Single-threaded execution is a suboptimal option due to CMPs' lower single-core performance, while multithreaded execution relies on prior parallelization, which is severely hampered by the low-level binary representation of applications compiled and optimized for a single-core target. A recent technology to address this problem is Dynamic Binary Parallelization (DBP), which creates a Virtual Execution Environment (VEE) taking advantage of the underlying multicore host to transparently parallelize the sequential binary executable. While still in its infancy, DBP has received broad interest within the research community. The combined use of DBP and thread-level speculation (TLS) has been proposed as a technique to accelerate legacy uniprocessor code on modern CMPs. In this paper, we investigate the limits of DBP and seek to gain an understanding of the factors contributing to these limits and the costs and overheads of its implementation. We have performed an extensive evaluation using a parameterizable DBP system targeting a CMP with light-weight architectural TLS support. We demonstrate that there is room for a significant reduction of up to 54% in the number of instructions on the critical paths of legacy SPEC CPU2006 benchmarks. However, we show that it is much harder to translate these savings into actual performance improvements, with a realistic hardware-supported implementation achieving a speedup of 1.09 on average.

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“…Kotha et al [13] and Benoît et al [14] propose the method of parallelizing executable binary by way of translating machine code to an intermediate representation, and analyzing this code statically. This method is incapable of determining hot-spot loops, while this is possible with the Selftrans.…”

Section: Comparison With Auto Vectorization Of Gccmentioning

confidence: 99%

Automatic Vectorization by Runtime Binary Translation

Nakamura¹,

Miki²,

Oikawa

2011

2011 Second International Conference on Networking and Computing

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Today, most general desktop PCs uses processors that incorporate SIMD (Single Instruction Multiple Data) units. These SIMD units, however, are for the most part underutilized with the exception of a few multimedia applications. As a result, the processing power of modern processors is not fully unleashed. In this research, we propose a system that applies automatic vectorization techniques to binary code at runtime to increase the utilization ratio of SIMD units, which will speed up the execution of programs. We will refer to this system as Selftrans. Selftrans extracts parallelism from binary x86 machine code without requiring its source code, and translates it into a binary code that utilizes the SIMD units. This paper describes the design and implementation of Selftrans. We will show that Selftrans is (1) capable of automatic vectorization of binary machine code, (2) that SIMDization can significantly improve performance, and (3) that it is possible to perform architecture-specific optimization for various processors.

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Polyhedral parallelization of binary code

Cited by 18 publications

References 24 publications

Affine Parallelization of Loops with Run-Time Dependent Bounds from Binaries

Affine Parallelization of Loops with Run-Time Dependent Bounds from Binaries

Limits of region-based dynamic binary parallelization

Automatic Vectorization by Runtime Binary Translation

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