PolyBench: The First Benchmark for Polystores

Karimov, Jeyhun; Rabl, Tilmann; Markl, Volker

doi:10.1007/978-3-030-11404-6_3

Cited by 14 publications

(3 citation statements)

References 18 publications

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“…Benchmarking Benchmarking is the standard practice for detecting regressions in compilers. Popular benchmark suites for C/C++ include SPEC 2017 [6] and PolyBench [17]. Benchmarking can reveal the existence of regressions, track improvements, and identify performance bottlenecks on specific benchmarks with specific inputs.…”

Section: Related Workmentioning

confidence: 99%

Finding missed optimizations through the lens of dead code elimination

Theodoridis

Rigger

2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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Compilers are foundational software development tools and incorporate increasingly sophisticated optimizations. Due to their complexity, it is difficult to systematically identify opportunities for improving them. Indeed, the automatic discovery of missed optimizations has been an important and significant challenge. The few existing approaches either cannot accurately pinpoint missed optimizations or target only specific analyses. This paper tackles this challenge by introducing a novel, effective approach that Ð in a simple and general manner Ð automatically identifies a wide range of missed optimizations. Our core insight is to leverage dead code elimination (DCE) to both analyze how well compilers optimize code and identify missed optimizations: (1) insert łoptimization markersž in the basic blocks of a given program, (2) compute the program's live/dead basic blocks using the łoptimization markersž, and (3) identify missed optimizations from how well compilers eliminate dead blocks. We essentially exploit that, since DCE heavily depends on the rest of the optimization pipeline, through the lens of DCE, one can systematically quantify how well compilers optimize code. We conduct an extensive analysis of GCC and LLVM using our approach, which (1) provides quantitative and qualitative insights regarding their optimization capabilities, and (2) uncovers a diverse set of missed optimizations. Our results also lead to 84 bug reports for GCC and LLVM, of which 62 have already been confirmed or fixed, demonstrating our work's strong practical utility. We expect that the simplicity and generality of our approach will make it widely applicable for understanding compiler performance and finding missed optimizations. This work opens and initiates this promising direction. CCS CONCEPTS• Software and its engineering → Compilers.

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Section: Related Workmentioning

confidence: 99%

Finding missed optimizations through the lens of dead code elimination

Theodoridis

Rigger

2022

Proceedings of the 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems

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“…We conducted experiments by mapping 12 selected performance-critical loops from three benchmarks: 1) MiBench [26], 2) Spec2006 [27], and 3) PolyBench [28] suite for broad representation. In Table 1, we describe the DDGs converted from these loops in detail, where N op , N dep , N Mop , N M dep , D Mmax and D Mmin indicate the number of operators, the number of dependencies, the number of operators with mobilities, the number of long dependencies, the maximal dependence length (i.e., the number of control steps traversed by a dependence) and the minimal dependence length, respectively.…”

Section: Benchmarksmentioning

confidence: 99%

Routability-Enhanced Scheduling for Application Mapping on CGRAs

Zeng

Wang

2021

IEEE Access

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Coarse-Grained Reconfigurable Architectures (CGRAs) are a promising solution to domainspecific applications for their energy efficiency and flexibility. To improve performance on CGRA, modulo scheduling is commonly adopted on Data Dependence Graph (DDG) of loops by minimizing the Initiation Interval (II) between adjacent loop iterations. The mapping process usually consists of scheduling and placement-and-routing (P&R). As existing approaches don't fully and globally explore the routing strategies of the long dependencies in a DDG at the scheduling stage, the following P&R is prone to failure leading to performance loss. To this end, this paper proposes a routability-enhanced scheduling for CGRA mapping using Integer Linear Programming (ILP) formulation, where a global optimized scheduling could be found to improve the success rate of P&R. Experimental results show that our approach achieves 1.12× and 1.22× performance speedup, 28.7% and 50.2% compilation time reduction, as compared to 2 state-of-theart heuristics.INDEX TERMS Coarse-grained reconfigurable architectures (CGRAs), modulo scheduling, routing strategy, placement and routing (P&R)

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“…We randomly selected 17 benchmarks from three benchmark suites, 6 from Rodinia 3.1 [17], 6 from Polybench GPU-1.0 [18] and 5 from ISPASS 2009 benchmark suite. We filtered other benchmarks because their hit ratios of shared TLB are higher than 90%.…”

Section: Environment Setup Gpgpu-simmentioning

confidence: 99%

Compressed page walk cache

Zhang

Jia

Shen

2021

Front. Comput. Sci.

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GPUs are widely used in modern high-performance computing systems. To reduce the burden of GPU programmers, operating system and GPU hardware provide great supports for shared virtual memory, which enables GPU and CPU to share the same virtual address space. Unfortunately, the current SIMT execution model of GPU brings great challenges for the virtual-physical address translation on the GPU side, mainly due to the huge number of virtual addresses which are generated simultaneously and the bad locality of these virtual addresses. Thus, the excessive TLB accesses increase the miss ratio of TLB. As an attractive solution, Page Walk Cache (PWC) has received wide attention for its capability of reducing the memory accesses caused by TLB misses.However, the current PWC mechanism suffers from heavy redundancies, which significantly limits its efficiency. In this paper, we first investigate the facts leading to this issue by evaluating the performance of PWC with typical GPU benchmarks. We find that the repeated L4 and L3 indices of virtual addresses increase the redundancies in PWC, and the low locality of L2 indices causes the low hit ratio in PWC. Based on these observations, we propose a new PWC structure, namely Compressed Page Walk Cache (CPWC), to resolve the redundancy burden in current PWC. Our CPWC can be organized in either directmapped mode or set-associated mode. Experimental results show that CPWC increases by 3 times over TPC in the number of page table entries, increases by 38.3% over PWC in L2 index hit ratio and reduces by 26.9% in the memory accesses of page tables. The average memory accesses caused by each TLB miss is reduced to 1.13. Overall, the average IPC can improve by 25.3%.

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PolyBench: The First Benchmark for Polystores

Cited by 14 publications

References 18 publications

Finding missed optimizations through the lens of dead code elimination

Finding missed optimizations through the lens of dead code elimination

Routability-Enhanced Scheduling for Application Mapping on CGRAs

Compressed page walk cache

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