Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Shi, Ying; Ma, T.P.; Prasad, Sharad; Dhanda, Sumit Singh

doi:10.1109/16.726656

Cited by 112 publications

(10 citation statements)

References 8 publications

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“…The electron ͑from the gate͒ and hole ͑from the substrate͒ tunneling currents are measured with the source and drain physically tied to ground and the gate negatively biased. [15][16][17] In a Ge device, I S/D is lower and the portion of I SUB in I G is larger than that in the Si device due to ͑1͒ HfO 2 dielectric with larger equivalent oxide thickness; and ͑2͒ TiN metal electrode with free electrons. The hole and electron tunneling currents are measured using a Keithley 4200 dc characterization system.…”

Section: Methodsmentioning

confidence: 99%

Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

Choi

Numata

Nishida

et al. 2008

Journal of Applied Physics

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Articles you may be interested inFluorine implantation for effective work function control in p -type metal-oxide-semiconductor high-k metal gate stacks J. Vac. Sci. Technol. B 29, 01A905 (2011); 10.1116/1.3521471 Low temperature mobility in hafnium-oxide gated germanium p -channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 91, 263512 (2007); 10.1063/1.2828134 Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors Strain-induced changes in the gate tunneling currents in p -channel metal-oxide-semiconductor field-effect transistors Appl. Phys. Lett. 88, 052108 (2006); 10.1063/1.2168671Modeling and characterization of direct tunneling hole current through ultrathin gate oxide in pmetal-oxide-semiconductor field-effect transistors Uniaxial four-point wafer bending stress-altered gate tunneling currents are measured for germanium ͑Ge͒/silicon ͑Si͒ channel metal-oxide-semiconductor field-effect transistors ͑MOSFETs͒ with HfO 2 / SiO 2 gate dielectrics and TiN/ P+ poly Si electrodes. Carrier separation is used to measure electron and hole currents. The strain-altered hole tunneling current from the p-type inversion layer of Ge is measured to be ϳ4 times larger than that for the Si channel MOSFET, since the larger strain-induced valence band-edge splitting in Ge results in more hole repopulation into a subband with a smaller out-of-plane effective mass and a lower tunneling barrier height. The strain-altered electron tunneling current from the metal gate is measured and shown to change due to strain altering the metal work function as quantified by flatband voltage shift measurements of Si MOS capacitors with TaN electrodes.

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Section: Methodsmentioning

confidence: 99%

Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

Choi

Numata

Nishida

et al. 2008

Journal of Applied Physics

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“…Thus, I g current under off-state bias conditions can be reduced for the LTP device. In this case, direct hole tunneling from the inversion layer to the p þ poly-Si gate that is measured as the source-drain current (I sd ) by the carrier separation method 11) is almost the same by taking into account the slight difference in V fb between both devices as shown in Fig. 11.…”

Section: Device Characteristicsmentioning

confidence: 98%

Suppression of Gate Depletion in p⁺-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing

Yamamoto¹,

Kubo

Okabe

et al. 2005

Jpn. J. Appl. Phys.

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Laser thermal processing (LTP) was investigated as a gate pre-annealing technique and its advantages over rapid thermal annealing (RTA) with regard to both gate activation and suppression of boron penetration were confirmed by evaluating the electrical characteristics of sub-40 nm p-metal oxide semiconductor field effect transistors (pMOSFETs). Laser annealing transformed amorphous Si in which high doses of boron were implanted into poly-Si with highly activated boron profiles down to the gate/gate oxide interface. By suppressing gate depletion with suppressing boron penetration, LTP results in an on-current at I off=70 [nA/µm] that is 4% greater than that in a device fabricated using conventional RTA. The off-state I g current that flows mainly from the p+ poly-Si gate to the drain overlap region is smaller in devices fabricated using LTP because the reduced roughness of the poly-Si gate/gate oxide interface in these devices reduces the local electric field enhancement.

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“…Indeed, much less is known about the physical basis for m ox values widely ranging from 0:3m 0 to 0:86m 0 (where m 0 is the free electron mass). [7][8][9][10][11] For example, while p þ polygate pMOSFETs are measured in the inversion mode, there are two different inferences that explain the experimental data of Fowler-Nordheim (FN) tunneling by tuning both m ox and b . 9,10) The ambiguous inferences derived from the calculation of FN tunneling are closely related to the use of both m ox and b .…”

Section: Introductionmentioning

confidence: 99%

“…[7][8][9][10][11] For example, while p þ polygate pMOSFETs are measured in the inversion mode, there are two different inferences that explain the experimental data of Fowler-Nordheim (FN) tunneling by tuning both m ox and b . 9,10) The ambiguous inferences derived from the calculation of FN tunneling are closely related to the use of both m ox and b . In order to avoid the uncertainty of determining I-V fitting parameters, electron transport properties should be clarified using the quantum yield (QY) of impact ionization in silicon.…”

Section: Introductionmentioning

confidence: 99%

Analysis of Electron Tunneling Components in p⁺ Poly-Gate p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors from Direct Tunneling Region to Fowler–Nordheim Region

Kang¹,

Wu²

2007

jjap

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In this paper, we propose a method of analyzing electron tunneling components in the inversion mode of p+ poly-gate p-channel metal–oxide–semiconductor field-effect transistors from the direct tunneling (DT) region to the Fowler–Nordheim (FN) region. In order to avoid the uncertainty of determining tunneling current–voltage (I–V) fitting parameters, the quantum yield measurement at different gate oxide thicknesses can have potential applications in identifying the tunneling components as follows: (i) in the DT region, electron tunneling still originates from the valence band edge; and (ii) particularly in the FN region, interface-state-assisted FN tunneling dominates electron current and lies between the Fermi level and the valence band edge, instead of the Fermi level as a reference energy level proposed by Pompl et al. [European Solid-State Device Research Conf., 2000, p. 292]. This results in a revised voltage-dependent barrier height for the calculation of FN tunneling.

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Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Cited by 112 publications

References 8 publications

Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

Suppression of Gate Depletion in p⁺-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing

Analysis of Electron Tunneling Components in p⁺ Poly-Gate p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors from Direct Tunneling Region to Fowler–Nordheim Region

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Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Cited by 112 publications

References 8 publications

Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

Impact of mechanical stress on gate tunneling currents of germanium and silicon p-type metal-oxide-semiconductor field-effect transistors and metal gate work function

Suppression of Gate Depletion in p+-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing

Analysis of Electron Tunneling Components in p+ Poly-Gate p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors from Direct Tunneling Region to Fowler–Nordheim Region

Contact Info

Product

Resources

About

Suppression of Gate Depletion in p⁺-Polysilicon-Gated Sub-40 nm pMOSFETs by Laser Thermal Processing

Analysis of Electron Tunneling Components in p⁺ Poly-Gate p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors from Direct Tunneling Region to Fowler–Nordheim Region