Polar Codes Sequential Decoder Hardware Architecture

Krylov, Aleksei; Rashich, Andrey; Gelgor, Aleksandr; Fadeev, Dmitrii K.

doi:10.1109/tsp.2019.8769111

Cited by 7 publications

(3 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In logarithmic domain this algorithm uses two functions -namely Q-function and P function (Eq. 1) to traverse the decoding tree [14]. Decoding tree leafs are refered to codeword bits, and thus traversing the tree correspond to bit-by-bit succesive dedoding.…”

Section: Polar Codes Sequential Decoder a Sequential Decoding Algorithmmentioning

confidence: 99%

“…1 to calculate path metrics on each iterations. MP in [14] uses fully parallel structure in order to reduce the latency of one iteration and to avoid intermediate result storage that is proposed in [13].…”

Section: B General Sq Decoder Structurementioning

confidence: 99%

“…Sequential (SQ) decoder [12], [13] could be seen as a modification of SCS decoder that uses several ingenious improvements in order to reduce decoding latency. The basic hardware architecture of sequential decoder is proposed in [14]. One of the most important blocks in SQ decoder is the Priority Queue (PQ) or stack in terms of SCS decoder.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Priority Queue VLSI Architecture for Sequential Decoder of Polar Codes

Rashich¹,

Krylov²,

Fadeev³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

<div>The VLSI architectures for stack or priority queue (PQ) are required in the implementation of stack or sequential decoders of polar codes. Such type of decoders provide good BER performance keeping complexity low. Extracting the best and the worst paths from PQ is the most complex operation in terms of both latency and complexity, because this operation requires full search along priority queue. In this work we propose a low latency and low complexity parallel hardware architecture for PQ, which is based on the systolic sorter and simplified sorting primitives. The simulation results show that just small BER degradation is introduced compared to ideal full sorting networks. Proposed PQ architecture is implemented in FPGA, the synthesis results are presented for all components of PQ.</div>

show abstract

Section: Polar Codes Sequential Decoder a Sequential Decoding Algorithmmentioning

confidence: 99%

Section: B General Sq Decoder Structurementioning

confidence: 99%