PMCNOC: A Pipelining Multi-Channel Central Caching Network-on-Chip Communication Architecture Design

Wang, Hong; Sanusi, .; Zhao, Xiujian; Mohamed, A.S.R.; Bayoumi,

doi:10.1109/sips.2007.4387596

Cited by 3 publications

(3 citation statements)

References 13 publications

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“…3 Previously Proposed CTCNOC Design [10] To address the problems of the existing architectures, we presented the Single-channel Central Caching NOC switch architecture (CTCNOC) as shown in Fig. 7.…”

Section: Vichar Router [28]mentioning

confidence: 99%

“…4 Proposed PMCNOC Architecture [11] For our PMCNOC architecture, input buffers are employed at the input channels; arbitration unit is responsible for making all the arbitration decisions; a dual port RAM is employed as the central cache which is partitioned into four segments (C0, C1, C2 and C3 for output port east, north, west and south respectively) accessible by the control unit as shown in Fig. 9 where n is the size of the cache segments.…”

Section: Latencies Vs Throughputmentioning

confidence: 99%

“…Section 2 discusses works related to this study. Section 3 briefly talks about our previously proposed CTCNOC design [10]. Section 4 presents the new PMCNOC architecture design [11].…”

mentioning

confidence: 99%

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PMCNOC: A Pipelining Multi-channel Central Caching Network-on-chip Communication Architecture Design

Wang

Sanusi

Zhao

et al. 2009

J Sign Process Syst

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With the de facto transformation of technology into nano-technology, more and more functional components can be embedded on a single silicon die, thus enabling high degree pipelining operations such as those required for multimedia applications. In recent years, system-on-chip designs have migrated from fairly simple single processor and memory designs to relatively complicated systems with multiple processors, on-chip memories, standard peripherals, and other functional blocks. The communication between these IP blocks is becoming the dominant critical system path and performance bottleneck of system-on-chip designs. Network-on-chip architectures, such as Virtual Channel (2004), Black-bus (2004), Pirate (2004), AEthereal (2005), and VICHAR (2006) architectures, emerged as promising solutions for future system-onchip communication architecture designs. However, these existing architectures all suffer from certain problems, including high area cost and communication latency and/ or low network throughput. This paper presents a novel network-on-chip architecture, Pipelining Multi-channel Central Caching, to address the shortcomings of the existing architectures. By embedding a central cache into every switch of the network, blocked head packets can be removed from the input buffers and stored in the caches temporally, thus alleviating the effect of head-of-line and deadlock problems and achieving higher network throughput and lower communication latency without paying the price of higher area cost. Experimental results showed that the proposed architecture exhibits both hardware simplicity and system performance improvement compared to the existing network-on-chip architectures.

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Section: Vichar Router [28]mentioning

confidence: 99%

Section: Latencies Vs Throughputmentioning

confidence: 99%