PLC Program Translation for Verification Purposes

Darvas, Dániel; Majzik, István; Viñuela, Enrique Blanco

doi:10.3311/ppee.9743

Cited by 17 publications

(25 citation statements)

References 11 publications

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“…Many works attempted to apply formal methods to the verification of PLC programs, mainly adopting model checking [2][3][4]6,7,9,11,[24][25][26][27][28][29][30][31][32][33]. Most of the work focused on the formal representation and verification of PLC programs written in one of the languages of the IEC 61131-3 standard.…”

Section: Related Workmentioning

confidence: 99%

“…[33] introduced a compositional approach to the multi-level behavior modeling and formal validation of large-scale distributed systems operations using hierarchies and networks of finite state automata. Meanwhile, the work in [11] mentioned that all PLC languages could be represented in ST, which can be verified by ST-based PLCverif model checking tools. These efforts all attempt to solve the modeling problem, but writing formal specifications is still difficult for engineers without related expertise.…”

Section: Related Workmentioning

confidence: 99%

“…However, since deductive verification requires strong professional knowledge and heavy manual work, it is still not widely used in practice. Therefore, most research works focus on model checking of PLC [3][4][5][6][7][8][9][10][11][12]. Almost all of them follow the following pattern: firstly, transforming the PLC program written in one specific PLC language into some formal model; secondly, expressing the system property in a specific formal language which is not ambiguous (The formal expression of the property is usually called formal specification.…”

Section: Introductionmentioning

confidence: 99%

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A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

et al. 2020

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Programmable logic controllers (PLCs) are special embedded computers that are widely used in industrial control systems. To ensure the safety of industrial control systems, it is necessary to verify the correctness of PLCs. Formal verification is considered to be an effective method to verify whether a PLC program conforms to its specifications, but the expertise requirements and the complexity make it hard to be mastered and widely applied. In this paper, we present a specification-mining-based verification approach for IEC 61131-3 PLC programs. It only requires users to review specifications mined from the program behaviors instead of model checking for specified specifications, which can greatly improve the efficiency of safety verification and is much easier for control system engineers to use. Moreover, we implement a proof-of-concept tool named PLCInspector that supports directly mining LTL specifications and data invariants from PLC programs. Two examples and one real-life case study are presented to illustrate its practicability and efficiency. In addition, a comparison with the existing verification approaches for PLC programs is discussed.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

et al. 2020

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“…Formal verification is essential during the conception of critical automated systems [1]. Several techniques are available for checking properties about such systems: theorem proof, test, simulation and model-checking [2].…”

Section: Introductionmentioning

confidence: 99%

SE-LTL Model-checking on Timed GRAFCETS via ε-TPN

Sogbohossou

Yehouessi

Djara

et al. 2019

CJAST

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The GRAFCET standard (IEC 60848) is one of the convenient formalisms used to specify the behaviour of the automated systems. Being just a semi-formal language, the usual practice is to go through an unambiguous formalism such as time Petri net (TPN) in order to validate a specification expressed by a GRAFCET model. In this paper, we propose how to perform model-checking on a GRAFCET model translated into a ε-TPN, specifically with State-Event Linear Temporal Logic (SE-LTL). Especially, we provide a way to take into account quantitative time constraints verification by integrating observers in the ε-TPN intermediate model, since TPN state-space abstractions do not allow directly such kind of model-checking.

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“…This introduction of the human factor into model checking reduces its reliability. One possible remedy is to obtain formal models directly from the source code of the system [4], but this is not possible (1) when the modeled components describe the plant, not the controller, and (2) when the source code is closed to the analysts [5]. An alternative approach is to apply formal synthesis techniques [6]- [11], but they have computational limitations which often make them inapplicable in practice, and their output is difficult for a human to understand.…”

Section: Introductionmentioning

confidence: 99%

Synthesis-Aided Reliability Assurance of Basic Block Models for Model Checking Purposes

Buzhinsky

Pakonen

Vyatkin

2018

2018 IEEE 27th International Symposium on Industrial Electronics (ISIE)

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In the Finnish nuclear industry, model checking, a formal verification technique, is used as an additional means of safety assurance for instrumentation and control (I&C) system design. Since the code of vendor-specific basic function blocks used in I&C is commonly closed, these blocks need to be modeled manually based on available specification. This modeling introduces an additional source of human factor into the verification process. To increase the reliability of the library of basic blocks used in nuclear I&C verification, we apply formal synthesis techniques, which can construct finite-state models of reactive systems from behavior examples and temporal properties. Since these techniques have computational limitations and synthesized models are hard to understand even by an analyst, we do not use them in the final verification process. Instead, in an iterative process, behavioral differences between a synthesized model and a manual model implementation are identified and used to create a list of features of manual implementations which either violate the specification or show that the specification is ambiguous.

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PLC Program Translation for Verification Purposes

Abstract: Abstract

Cited by 17 publications

References 11 publications

A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

A User-Friendly Verification Approach for IEC 61131-3 PLC Programs

SE-LTL Model-checking on Timed GRAFCETS via ε-TPN

Synthesis-Aided Reliability Assurance of Basic Block Models for Model Checking Purposes

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