Platform Storage Performance With 3D XPoint Technology

Hady, Frank; Foong, Annie; Veal, Bryan; Williams, Dan

doi:10.1109/jproc.2017.2731776

Cited by 189 publications

(69 citation statements)

References 10 publications

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“…The 3D XP memory shown in Fig. 2 [25] is been a promising direction to solve this bottleneck, and the major issue that remains is the device to device variability of the resistive state. Even with variability, the neural networks have shown robust performances, as during the learning phase, any variability in the states translates to the variability in weights, which are compensated by the learning algorithm to find the optimal set of weights that works best for the given neural network configuration.…”

Section: Edge Devices and Emerging Neural Computingmentioning

confidence: 99%

Neuromemristive Circuits for Edge Computing: A Review

Krestinskaya

James

Chua

2020

IEEE Trans. Neural Netw. Learning Syst.

219

120

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The volume, veracity, variability and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing.

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Section: Edge Devices and Emerging Neural Computingmentioning

confidence: 99%

Neuromemristive Circuits for Edge Computing: A Review

Krestinskaya

James

Chua

2020

IEEE Trans. Neural Netw. Learning Syst.

219

120

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“…The B-APM technology that will be the first to market is Intel and Microns 3D XPoint TM memory [5]. The performance of this, byte-addressable, B-APM, is projected to be lower than main memory (with a latency ∼5-10x that of DDR4 memory when connected to the same memory channels), but much faster than SSDs or HDDs.…”

Section: Persistent Memorymentioning

confidence: 99%

An Architecture for High Performance Computing and Data Systems Using Byte-Addressable Persistent Memory

Jackson

Weiland

Parsons

et al. 2019

Lecture Notes in Computer Science

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Non-volatile, byte addressable, memory technology with performance close to main memory promises to revolutionise computing systems in the near future. Such memory technology provides the potential for extremely large memory regions (i.e. > 3TB per server), very high performance I/O, and new ways of storing and sharing data for applications and workflows. This paper outlines an architecture that has been designed to exploit such memory for High Performance Computing and High Performance Data Analytics systems, along with descriptions of how applications could benefit from such hardware.

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“…Instead, a time required for OS processing has become a primary overhead in the I/O latency due to the low device latency. Although a lot of optimization techniques have been implemented to reduce this OS overhead, it is still non-trivial for low-latency SSDs [2].…”

Section: Introductionmentioning

confidence: 99%

Reducing CPU Power Consumption with Device Utilization-Aware DVFS for Low-Latency SSDs

Imamura

Yoshida

2019

IEICE Trans. Inf. & Syst.

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Emerging solid state drives (SSDs) based on a nextgeneration memory technology have been recently released in market. In this work, we call them low-latency SSDs because the device latency of them is an order of magnitude lower than that of conventional NAND flash SSDs. Although low-latency SSDs can drastically reduce an I/O latency perceived by an application, the overhead of OS processing included in the I/O latency has become noticeable because of the very low device latency. Since the OS processing is executed on a CPU core, its operating frequency should be maximized for reducing the OS overhead. However, a higher core frequency causes the higher CPU power consumption during I/O accesses to low-latency SSDs. Therefore, we propose the device utilization-aware DVFS (DU-DVFS) technique that periodically monitors the utilization of a target block device and applies dynamic voltage and frequency scaling (DVFS) to CPU cores executing I/O-intensive processes only when the block device is fully utilized. In this case, DU-DVFS can reduce the CPU power consumption without hurting performance because the delay of OS processing incurred by decreasing the core frequency can be hidden. Our evaluation with 28 I/O-intensive workloads on a real server containing an Intel R Optane TM SSD demonstrates that DU-DVFS reduces the CPU power consumption by 41.4% on average (up to 53.8%) with a negligible performance degradation, compared to a standard DVFS governor on Linux. Moreover, the evaluation with multiprogrammed workloads composed of I/O-intensive and non-I/O-intensive programs shows that DU-DVFS is also effective for them because it can apply DVFS only to CPU cores executing I/O-intensive processes.

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Platform Storage Performance With 3D XPoint Technology

Cited by 189 publications

References 10 publications

Neuromemristive Circuits for Edge Computing: A Review

Neuromemristive Circuits for Edge Computing: A Review

An Architecture for High Performance Computing and Data Systems Using Byte-Addressable Persistent Memory

Reducing CPU Power Consumption with Device Utilization-Aware DVFS for Low-Latency SSDs

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