2005
DOI: 10.1109/tcad.2005.852431
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Abstract: International audienceThis paper presents Disydent, a framework dedicated to system-on-a-chip (SoC) platform-based design for shared memory multiple instructions multiple data (MIMD) architectures. We define a platform-based design problem as a triplet (system, application, constraints) where the system is both an operating system (OS) and a hardware (HW) template that can be enhanced with dedicated coprocessors. Our contributions are: 1) the definition of a complete flow for platform-based design, from applic… Show more

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Cited by 46 publications
(24 citation statements)
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“…The above some Cache optimization technologies such as target application, design, optimization and carried on the simple classification, as shown in Table 1 Dynamic spillover receiver(DSR, [9]) Distributed cooperation Cache [20] Shared design Improve the hit access speed…”
Section: E Cmp Stage Cache Optimization Technology Classificationmentioning
confidence: 99%
See 1 more Smart Citation
“…The above some Cache optimization technologies such as target application, design, optimization and carried on the simple classification, as shown in Table 1 Dynamic spillover receiver(DSR, [9]) Distributed cooperation Cache [20] Shared design Improve the hit access speed…”
Section: E Cmp Stage Cache Optimization Technology Classificationmentioning
confidence: 99%
“…On one hand the speed gap between processor and memory is growing; on the other hand, the limited bandwidth will increasingly make the program performance depends on the on-chip memory hierarchy [20]. Therefore, designers will design the last level cache design large enough to save more data on chip.…”
Section: Introductionmentioning
confidence: 99%
“…Several execution platforms for KPN applications were proposed [6]- [10], [15], [16]. The approach in [16] does not support multi-application execution.…”
Section: Related Workmentioning
confidence: 99%
“…The approach in [16] does not support multi-application execution. The platform in [15] executes KPN processes by scheduling them on reconfigurable accelerators.…”
Section: Related Workmentioning
confidence: 99%
“…Using proprietary specification formats, and targeting specific applications domain (e.g. DSP) or hardware architecture templates is found in [4], [5], and [6]. High-level synthesis tasks such as the scheduling optimizations have been studied in [1], [7], [8], [9].…”
Section: Related Workmentioning
confidence: 99%