Plasma-etching profile model for SiO/sub 2/ contact holes

Liu, Chunli; Abraham‐Shrauner, Barbara

doi:10.1109/tps.2002.804166

Cited by 7 publications

(2 citation statements)

References 42 publications

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“…Due to the microloading phenomenon, a small contact hole causes a shallow etch and retains thick remaining oxide. 18,19) Figure 2 shows a comparison of the read current characteristics of the fresh cells with reduced programmable contact sizes, where the initial read current can be effectively suppressed. The reason for this is that the leakage depends on the remaining oxide thickness, especially the leakage current from direct tunneling method in the thinner remaining oxide.…”

Section: Programmable Contact Sizingmentioning

confidence: 99%

Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process

Huang

Tseng

Kuo

et al. 2010

Jpn. J. Appl. Phys.

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A multilevel oxide antifuse cell with programmable contact, fully compatible with a standard complementary metal-oxide-semiconductor (CMOS) logic process, is firstly presented for logic nonvolatile memory applications. A four-state antifuse cell has a stable read window and a very small cell size of 0.097 mm 2 /bit. By adopting the multiple stages in oxide breakdown, four states of read current level have been successfully demonstrated on this cell fabricated by a standard 90 nm CMOS logic process. A fast programming speed of 10 ms can be obtained using a low programming voltage of less than 4 V. With excellent technology scalability and adaptability, this multilevel antifuse cell provides a very promising solution for programmable logic beyond a 90 nm technology node.

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Section: Programmable Contact Sizingmentioning

confidence: 99%

Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process

Huang

Tseng

Kuo

et al. 2010

Jpn. J. Appl. Phys.

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“…27,49,50) The predominant ion is pressumed to be CF 3 þ in CF 4 plasmas, where the relative abundance of CF 3 þ , CF 2 þ , and CF þ depends on feed gas density as well as on plasma electron density and temperature. 51) To investigate the role of mask geometry on etched profiles such as undercut, bowing, and RIE lag, profile evolution was simulated using the Monte Carlo and cell removal methods. The model is described in §2, and the numerical results of the etched feature profiles are presented in §3.…”

Section: Introductionmentioning

confidence: 99%

Effects of Mask Pattern Geometry on Plasma Etching Profiles

Fukumoto

Eriguchi

Ono

2009

Jpn. J. Appl. Phys.

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Two-dimensional etching profile evolution in two different geometries, namely an axisymmetric hole and an infinitely long trench, has been simulated with the cellular algorithm, to clarify the effects of geometrically different structures on etching profile evolution. The simulation assumed SiO 2 etching using CF 4 plasmas, owing to the widely employed fluorocarbon plasmas for the fabrication of contact and via holes. Numerical results indicated that the two mask pattern geometries give some differences in profile evolution, depending on condition parameters such as ion energy, mask pattern size, mask height, and reflection probability on mask surfaces. The profile evolution is slower and more anisotropic in a hole than in a trench; in practice, the profile of a trench tends to have prominent lateral etches such as an undercut and a bowing on sidewalls. Moreover, the reactive ion etching lag is less significant for a hole than for a trench. These differences are ascribed to the geometrical shadowing effects of the structure for neutrals, where the incident flux of neutrals is more significantly reduced in a hole than in a trench. The differences are also attributed to the anisotropy of the velocity distribution of neutrals; in effect, the velocity distribution is more anisotropic in a hole, because more particles interact with mask sidewalls to adsorb or reflect thereon in a hole, so that more anisotropic neutrals are transported onto bottom surfaces after passing mask features.

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Review of profile and roughening simulation in microelectronics plasma etching

Wei¹,

Sawin²

2009

J. Phys. D: Appl. Phys.

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Plasma etching of thin films is essential for microelectronics manufacturing. With current feature sizes of 35 nm in production and processes for smaller devices being developed, the sidewall roughness is within the order of magnitude of the gate length of the device, and therefore significantly impacts the devices' performance. In this paper we review the modelling of the surface profile evolution in plasma etching. Both two-dimensional (2D) and three-dimensional (3D) models have been developed using a number of representations and solution algorithms. String algorithms and the method of characteristics use a segmented string which is incrementally advanced. Level-set representations describe the profile evolution as a moving interface in response to a velocity field. Cellular representations in which the area or volume domain is divided into discrete cells have been used with flux and surface kinetics based on Monte Carlo calculations. We discuss our work in the modelling of profile evolution with surface roughening using a 3D cellular Monte Carlo simulation. The formation of perpendicular and parallel ripple formation on planar surfaces as a function of ion bombardment incidence angle and the transformation from perpendicular to parallel as etching progresses has been modelled. The smoothing and/or roughening of resist masks has been demonstrated along with the pattern transfer of roughness into the underlying layers being etched.

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Plasma-etching profile model for SiO/sub 2/ contact holes

Cited by 7 publications

References 42 publications

Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process

Multilevel Antifuse Cells with Programmable Contact in Pure 90 nm Logic Process

Effects of Mask Pattern Geometry on Plasma Etching Profiles

Review of profile and roughening simulation in microelectronics plasma etching

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