Piton: A Manycore Processor for Multitenant Clouds

McKeown, Michael; Fu, Yaosheng; Nguyen, Tri Minh; Zhou, Yanqi; Balkind, Jonathan; Lavrov, Alexey; Shahrad, Mohammad; Payne, Samuel H.; Wentzlaff, David

doi:10.1109/mm.2017.36

Cited by 16 publications

(7 citation statements)

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“…GPUs feature thousands of compute units, but their utilization is limited by the SIMT regime. Especially for irregular and non-data-oblivious algorithms, thread divergence and RAW [24] 32-bit MIPS-style -16 ✓ ✓ ✓ × × × × × × Celerity [25] 32-bit RISC-V -496 * ✓ ✓ ✓ × × × ✓ ✓ ✓ KiloCore [26] 40-bit RISC -1000 ✓ ✓ ✓ × × × × × × Piton [27] 64-bit SPARC V9 -25 ✓ ✓ ✓ × × × ✓ ✓ ✓ TILE64 [28] 64-bit VLIW -64 ✓ ✓ ✓ × × × × × × Epiphany-V [29] 64-bit RISC -1024 ✓ ✓ ✓ × × × × × × Pixel Visual Core [6] 16-bit VLIW 256 2048 × × × × × × × × × crossbar-based GAP9 [11] 32-bit RISC-V 9 9 ✓ ✓ ✓ ✓ ✓ ✓ ≈ ≈ ≈ RC64 [13] 32-bit VLIW 64 64 ✓ ✓ ✓ ✓ ✓ ✓ × × × Manticore [14] 32-bit RISC-V 8 4096 ✓ ✓ ✓ × × × ✓ ✓ ✓ MPPA3 [12] 64-bit VLIW 16 80 ✓ ✓ ✓ × × × × × × ET-SoC-1 [15] 64-bit RISC-V 32 1088 ✓ ✓ ✓ × × × × × × H1000 [4] 32/64-bit PTX 128 18432 synchronization restrict the GPU's performance. In contrast, MemPool gives each PE its instruction stream, making it much more flexible and efficient on irregular workloads.…”

Section: Related Workmentioning

confidence: 99%

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory

Riedel,

Cavalcante,

Andri

et al. 2023

IEEE Trans. Comput.

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Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common belief that these tightly-coupled clusters would not scale beyond a few tens of PEs. In this work, we tackle scaling shared L1 clusters to hundreds of PEs while supporting a flexible and productive programming model and maintaining high efficiency. We present MemPool, a manycore system with 256 RV32IMAXpulpimg "Snitch" cores featuring application-tunable functional units. We designed and implemented an efficient low-latency PE to L1-memory interconnect, an optimized instruction path to ensure each PE's independent execution, and a powerful DMA engine and system interconnect to stream data in and out. MemPool is easy to program, with all the cores sharing a global view of a large, multi-banked, L1 scratchpad memory, accessible within at most five cycles in the absence of conflicts. We provide multiple runtimes to program MemPool at different abstraction levels and illustrate its versatility with a wide set of applications. MemPool runs at 600 MHz (60 gate delays) in typical conditions (TT/0.80 V/25 °C) in 22 nm FDX technology and achieves a performance of up to 229 GOPS or 180 GOPS/W with less than 2% of execution stalls.

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Section: Related Workmentioning

confidence: 99%

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory

Riedel,

Cavalcante,

Andri

et al. 2023

IEEE Trans. Comput.

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“…The Piton processor prototype 12,13 was manufactured in March 2015 on IBM's 32 nm SOI process with a target clock frequency of 1GHz. It features 25 tiles in a 5 × 5 mesh on a 6mm × 6mm (36 mm 2 ) die.…”

Section: The Princeton Piton Processormentioning

confidence: 99%

“…OpenPiton enables research from the small to the large with demonstrated implementations from the slimmed-down, single-core PicoPiton, which is emulated on a $160 Xilinx Artix 7 at 29.5MHz, up to the 25-core Piton processor which targeted a 1GHz operating point and was recently validated and thoroughly characterized. 12,13 The OpenPiton platform shown in Figure 1 is a modern, tiled, manycore design consisting of a 64-bit architecture using the mature SPARC v9 ISA with P-Mesh: our scalable cache coherence protocol and network on chip (NoC). OpenPiton builds upon the industry-hardened, open-source OpenSPARC T1 15,1,18 core, but sports a completely scratchbuilt uncore (caches, cache-coherence protocol, NoCs, NoC-based I/O bridges, etc), a new and modern simulation framework, configurable and portable FPGA scripts, a complete set of scripts enabling synthesis and implementation of ready-to-manufacture chips, and full-stack multiuser Debian Linux support.…”

Section: Introductionmentioning

confidence: 99%

OpenPiton

Balkind

McKeown

et al. 2019

Commun. ACM

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Industry is building larger, more complex, manycore processors on the back of strong institutional knowledge, but academic projects face difficulties in replicating that scale. To alleviate these difficulties and to develop and share knowledge, the community needs open architecture frameworks for simulation, chip design, and software exploration that support extensibility, scalability, and configurability, alongside an established base of verification tools and supported software. In this article, we present OpenPiton, an open source framework for building scalable architecture research prototypes from one core to 500 million cores. OpenPiton is the world's first open source, general-purpose, multithreaded manycore processor, and framework. OpenPiton is highly configurable, providing a rich design space spanning a variety of hardware parameters that researchers can change. OpenPiton designs can be emulated on FPGAs, where they can run full-stack multiuser Debian Linux. OpenPiton is designed to scale to very large core fabrics, enabling researchers to measure operating system, compiler, and software scalability. The mature codebase reflects the complexity of an industrial-grade design and provides the necessary scripts to build new chips, making OpenPiton a natural choice for computer-aided design (CAD) research. OpenPiton has been validated with a 25-core chip prototype, named Piton, and is bolstered by a validation suite that has thousands of tests, providing an environment to test new hardware designs while verifying the correctness of the whole system. OpenPiton is being actively used in research both internally to Princeton and in the wider community, as well as being adopted in education, industry, and government settings.

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“…Similar to our work, Morpheus [30] has exploited lowered performance variance to improve cluster utilization, but through automated SLOs as opposed to market incentives. Finally, many solutions have been proposed at the architecture-level to enable better utilization of underlying cloud processors [7,47]. 2) Self-Adaptation and Graceful Degradation.…”

Section: Related Workmentioning

confidence: 99%

Incentivizing self-capping to increase cloud utilization

Shahrad

Klein

Zheng

et al. 2017

Proceedings of the 2017 Symposium on Cloud Computing

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Cloud Infrastructure as a Service (IaaS) providers continually seek higher resource utilization to better amortize capital costs. Higher utilization not only can enable higher proit for IaaS providers but also provides a mechanism to raise energy eiciency; therefore creating greener cloud services. Unfortunately, achieving high utilization is diicult mainly due to infrastructure providers needing to maintain spare capacity to service demand luctuations.Graceful degradation is a self-adaptation technique originally designed for constructing robust services that survive resource shortages. Previous work has shown that graceful degradation can also be used to improve resource utilization in the cloud by absorbing demand luctuations and reducing spare capacity. In this work, we build a system and pricing model that enables infrastructure providers to incentivize their tenants to use graceful degradation. By using graceful degradation with an appropriate pricing model, the infrastructure provider can realize higher resource utilization while simultaneously, its tenants can increase their proit. Our proposed solution is based on a hybrid model which guarantees both reserved and peak on-demand capacities over lexible periods. It also includes a global dynamic price pair for capacity which remains uniform during each tenant's Service Level Agreement (SLA) term.We evaluate our scheme using simulations based on real-world traces and also implement a prototype using RUBiS on the Xen hypervisor as an end-to-end demonstration. Our analysis shows that the proposed scheme never hurts a tenant's net proit, but can improve it by as much as 93%. Simultaneously, it can also improve the efective utilization of contracts from 42% to as high as 99%.

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Piton: A Manycore Processor for Multitenant Clouds

Cited by 16 publications

References 0 publications

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory

OpenPiton

Incentivizing self-capping to increase cloud utilization

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