Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

Dusa, Mircea V.; Quaedackers, John; Larsen, Olaf F. A.; Meessen, Jeroen; Heijden, E. van der; Dicker, Gerald; Wismans, Onno; Haas, Paul de; Schenau, Koen van Ingen; Finders, Jo; Vleeming, Bert; Storms, Greet; Jaenen, Patrick; Cheng, Stone; Maenhoudt, Mireille

doi:10.1117/12.714278

Cited by 81 publications

(48 citation statements)

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“…Table 2 summarizes timing libraries that we generate for bimodal-aware timing analysis. Unimodal CD values corresponding to the bimodal CD values follow the calculation used in [6]. With the unimodal timing models, we require one timing signoff, while with the bimodal timing models, we need two timing signoffs, one for each of the G1L − G2S and G1S − G2L cases.…”

Section: Methodsmentioning

confidence: 99%

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Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Coskun

Kahng

Rosing

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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Double patterning lithography (DPL) is a likely resolution enhancement technique for IC production in 32nm and below technology nodes. However, DPL gives rise to two independent, uncorrelated distributions of linewidth on a chip, resulting in a 'bimodal' linewidth distribution and an increase in performance variation. [13] suggested that new physical design mechanisms could reduce harmful covariance terms that contribute to this performance variation.In this paper, we propose new bimodal-aware timing analysis and optimization methods to improve timing yield of standardcell based designs that are manufactured using DPL. Our first contribution is a DPL-aware approach to timing modeling, based on detailed analysis of cell layouts. Our second contribution is an ILP-based maximization of 'alternate' mask coloring of instances in timing-critical paths, to minimize harmful covariance and performance variation. Third, we propose a dynamic programming-based detailed placement algorithm that solves mask coloring conflicts and can be used to ensure "double patterning correctness" after placement or even after detailed routing, while minimizing the displacement of timing-critical cells with manageable ECO impact.With a 45nm library and open-source design testcases, our timing-aware recoloring and placement optimizations together achieve up to 232ps (resp. 36.22ns) reduction in worst (resp. total) negative slack, and 78% (resp. 65%) reduction in worst (resp. total) negative slack variation.

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Section: Methodsmentioning

confidence: 99%

“…Dusa et al [6] observe ∼8% mean CD difference between two poly groups in a double patterning process, with the two CD populations being uncorrelated to each other.…”

Section: Variations Are Caused By Overlay Error In (A) and By Spacmentioning

confidence: 99%

Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures

Coskun

Kahng

Rosing

2009

2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools

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“…Section IV then describes potential courses of action for the industry as standards and flows are evolved to address the bimodal challenge, and finally, Section V gives conclusions. Figure 4(a) shows a bimodal CD distribution for 32nm technology measured from 24 wafers processed by DPL, as reported in [4]. …”

Section: Double Patterning Dplmentioning

confidence: 99%

“…The topography implies greater depth of focus (DOF) variation, so that the CDs between the first and the second patterns can differ. Plasma exposure of the first line during the second etch could additionally cause CD change [4]. For these reasons, CDs of critical features will have a bimodal distribution.…”

Section: Double Patterning Dplmentioning

confidence: 99%

“…Double exposure DPL with negative tone resist creates trenches at twice the resolution of normal lithography, using two successive exposure steps. Double exposure DPL prints spaces rather than target line shapes, and is hence called a negative dual trench process [4]. One edge of a target line is formed with the first exposure, and the other edge is generated with the second exposure, as shown in Figure 1.…”

Section: Introduction Double Patterning Lithography (Dpl)mentioning

confidence: 99%

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Communication modeling for system-level design

Kahng

Samadi

2008

2008 International SoC Design Conference

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Abstract-Double patterning lithography (DPL) is in current production for memory products, and is widely viewed as inevitable for logic products at the 32nm node. DPL decomposes and prints the shapes of a critical-layer layout in two exposures. In traditional single-exposure lithography, adjacent identical layout features will have identical mean critical dimension (CD), and spatially correlated CD variations. However, with DPL, adjacent features can have distinct mean CDs, and uncorrelated CD variations. This introduces a new set of 'bimodal' challenges for timing analysis and optimization. We assess the potential impact of DPL on timing analysis error and guardbanding, and find that the traditional 'unimodal' characterization and analysis framework may not be viable for DPL. For example, using 45nm models, we find that different DPL mask layout solutions can cause 50ps skew in clock distribution that is unseen by traditional analyses. Different mask layouts can also result in 20% or more change in timing path delays. Such results lead to insights into physical design optimizations for clock and data path placement and mask coloring that can help mitigate the error and guardband costs of DPL.

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