Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory

Abstract

Abstract.A high speed security algorithm is always important for wired/wireless environment. The KeywordsAES pipelining, Key pipelining, Search Based Memory, VLSI. 1.IntroductionNetwork security has three major security goals: confidentiality, availability and message integration between senders and receivers . Many algorithms are available in each of these three goals of security. One of the frequently used security algorithm in block cipher is the AES algorithm [3]. High speed security decisions are important in order to support multimedia data transmission. VOIP needs fast security algorithm to guarantee Qos in real-time voice transmission [10], [11].Pipelining is an approach to increase the throughput of AES encryption and decryption algorithm. Speed of AES encryption depends on the number of rounds and the key generation involved in the algorithm. AES uses its own key expansion algorithm. Pipelined AES encryption and key pipelining in AES algorithm can increase the throughput of the algorithm.Like encryption and decryption module another important component of AES algorithm is its key expansion module. Both of encryption and decryption module depends mainly on this key expansion module. This key expansion algorithm is based on iterative looping architecture [3]. If the architecture for AES with basic iterative architecture and partial loop unrolling is compared, the loop unrolling increases the speed of rounds implementation than the single round implementation in AES key expansion algorithm [4].Speed called as encryption throughput is the primary optimization criteria. The large change of the throughput ratio can be explained by the use of block RAMs in AES implementations. Blocks RAMs are used for S-Box implementation. Depending upon the searching process on this block RAMs the speed of S-box substitution is done in one of the four modules of a round. This search based memory is applied to the S-box in AES rounds implementation [5].

An integrated approach for enhancing data security

“…A Hardware implementation of the AES was used for Encryption and Decryption. [5]. A framework containing four different modules namely Public key-Public key technique, Public key-Private key technique, Private Key-Public key technique and Private Key-Private key technique was used for data security.…”

Design and Implementation A different Architectures of mixcolumn in FPGA

“…There exist many presentations of hardware implementations of AES algorithms in literature. [32]. Unfortunately, most of those implementations are too costly for practical applications.…”