Pipelined recursive modified Euclidean algorithm block for low-complexity, high-speed Reed–Solomon decoder

Lee, H.; Azam, A.

doi:10.1049/el:20030886

Cited by 3 publications

(3 citation statements)

References 5 publications

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“…Comparing (1)-(4) with (5)- (8), it can be observed that they are different only in the positions of R i and Q i , L i and U i , and a i and b i ; thus, a potential internal switch signal can transfer (5)-(8) to (1)-(4) when the degree of R i is smaller than the degree of Q i without l i . Moreover, since multiplying x |l i | can be implemented by the shift operation, if the needed shift signal can be generated by the internal finite-state machine (FSM),…”

Section: B Kes Blockmentioning

confidence: 99%

“…In [3], the BM algorithm is reformulated as reformulated inversionless BM (RiBM) with the same regular architecture format compared with the conventional ME algorithm [4], [5], and a folded BM algorithm based on RiBM is introduced in [6]. References [4], [7], and [8] implemented the conventional ME algorithm with systolic and recursive architectures, and [5] and [9] further implemented the ME algorithm with higher speed and lower hardware complexity. Recently, the degree computationless modified Euclidean (DCME) algorithm has been introduced in [ architecture.…”

Section: Introductionmentioning

confidence: 99%

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Area-efficient reed-solomon decoder design for optical communications

Yuan

Wang

et al. 2009

IEEE Trans. Circuits Syst. II

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A high-speed low-complexity Reed-Solomon (RS) decoder architecture based on the recursive degree computationless modified Euclidean (rDCME) algorithm is presented in this brief. The proposed architecture has very low hardware complexity compared with the conventional modified Euclidean and degree computationless modified Euclidean (DCME) architectures, since it can reduce the degree computation circuitry and replace the conventional systolic architecture that uses many processing elements (PEs) with a recursive architecture using a single PE. A highthroughput data rate is also facilitated by employing a pipelining technique. The proposed rDCME architecture has been designed and implemented using SMIC 0.18-μm CMOS technology. Synthesized results show that the proposed RS (255, 239) decoder requires only about 18K gates and can operate at 640 MHz to achieve a throughput of 5.1 Gb/s, which meets the requirement of modern high-speed optical communications.

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Section: B Kes Blockmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Area-efficient reed-solomon decoder design for optical communications

Yuan

Wang

et al. 2009

IEEE Trans. Circuits Syst. II

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“…Note that [20] has better NAE value than our design but its NPE value is only 10% of our design. On the other hand, the ASIC-type the pipelined recursive RS architecture [22], [23] is very area-efficient with high data throughput rate (6160 Mb/s). Hence, it has a very high NAE value.…”

Section: ) Performance Comparisonmentioning

confidence: 99%

Multi-symbol-sliced dynamically reconfigurable Reed-Solomon decoder design based on unified finite-field processing element

Hsu

Yeo

2006

IEEE Trans. VLSI Syst.

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Abstract-Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, most RS decoders are implemented as dedicated application-specified integrated circuits (ASICs) based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, the RS decoding operations are usually performed by using fine-grained processing elements (PE) controlled by a programmable digital signal processing (DSP) core, which provides high flexibility. In this paper, we propose a novel -PE multisymbol-sliced (MSS) RS datapath structure. The -PE RS architecture is a highly scalable design and can be dynamically reconfigured at 1-PE, 2-PE,. . .2-PE, and -PE modes to deliver necessary data throughput rate. With the help of the gated-clock scheme to turn off the idle PEs, the proposed runtime configurable ASIC design provides good tradeoff between the data throughput rate and the power consumption. Hence, it can save energy to extend the battery life of the portable devices. We demonstrate a prototyping design using 4 PEs by using UMC 0.18-m CMOS technology. The design can be dynamically reconfigured to be operated at 1-PE, 2-PE, and 4-PE modes, with performance of 140 Mb/s at 18.91 mW, 280 Mb/s at 28.77 mW, and 560 Mb/s at 48.47 mW, respectively. Compared with existing RS designs, the proposed -PE RS decoder has better normalized area/power efficiency than most DSP-type and ASIC-type RS designs. The reconfigurable feature makes our design a good candidate for the error control coding (ECC) unit of the storage system in power-aware portable devices.

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Review of FPGA Implementation of Reed-Solomon Encoder-Decoder

Babrekar¹,

Sakhare²

2014

IJCA

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An important function of any modern digital communication system is error control coding (ECC). Such coding is the field of communications that deals with techniques for detecting and correcting errors in a signal. ECC is especially useful in wireless communication systems. RS codes are the most powerful in the family of linear block codes and are arguably the most widely used type of error control codes. RS code is a type of Forward Error Correction (FEC) code and it is a nonbinary, linear and cyclic block error correcting code. In this paper, the proposed work is to implement the encoder and decoder of Reed-Solomon (RS) coding scheme on the platform of VLSI using the Euclid's algorithm. Implementation will be done on VLSI Hardware Description Language (VHDL) and the operation and results can be seen on Field Programmable Gate Array (FPGA).

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Pipelined recursive modified Euclidean algorithm block for low-complexity, high-speed Reed–Solomon decoder

Cited by 3 publications

References 5 publications

Area-efficient reed-solomon decoder design for optical communications

Area-efficient reed-solomon decoder design for optical communications

Multi-symbol-sliced dynamically reconfigurable Reed-Solomon decoder design based on unified finite-field processing element

Review of FPGA Implementation of Reed-Solomon Encoder-Decoder

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