Pipelined adders for ultralow-power wearables

Abstract

For continuous real-time monitoring of personal health, wearable devices are indispensable. The constraints of cost, power consumption, and limited device dimensions are the critical issues which need to be handled carefully while designing these battery-powered devices. The wearables employ high-end processors dedicated for complex signal processing. The core of every digital signal processor is its data path. The arithmetic units like adders constitute the core of data path and addressing unit. This work proposes a novel low-complexity asynchronous pipelined adder. The proposed design guarantees great savings in power and latency, which makes it a suitable candidate for low-power highspeed sophisticated wearables. The proposed design consumes a minimum power of 33.46 µW and offers a minimum propagation delay of 0.04 ns in comparison to state-of-art adders such as ripple carry adder (RCA), carry look ahead adder (CLA), and carry select adder (CSA). Thus, an area-delay-power efficient adder design guarantees high-end performance for wearables.

High Speed PS0 Micro-Pipelined Adder

“…So, for high speed operations, proposed circuit should be preferred. RCA [11] CLA [12] CSA [13] Dual rail domino logic pipelined adder [14] Proposed adder Power (mw) Figure 8 shows the graphical representation of propagation delays of various adder designs.…”

“…It offers the lowest propagation delay (0.868 E-09) @ 1.2V and has a transistor count of 145 which is49.6% less as compared to RCA.Our design guarantees great savings in power and latency, making it a perfect candidate for low power high speed wearable devices for IoT. RCA [11] CLA [12] CSA [13] Dual rail domino logic pipelined adder [14] Proposed RCA [11] CLA [12] CSA [13] Dual rail domino logic adder [14] Proposed adder Chart Title…”

“…Asynchronous designs occupy less power as compared to synchronous counter parts due to absence of global clock [10]. This work proposes an asynchronous pipelined adder and its performance has been compared with state-of-art adders [11][12][13][14].The pipelining is discussed in section 2. The explanation to the proposed design is given in section 3 with simulations and results in section 4.…”