Pipeline Optimization using a Cost Extension of Timed Petri Nets

Abstract

A major step in arithmetic operators design is the placement of pipeline stages, with the goal of drastically increase the data throughput.Approaches, such as the as-soon-as-possible greedy algorithm, allow pipelining with a frequency target. They can possibly be combined with a retiming operation to reduce the number of pipeline registers. This retiming step is based on a weighted directed graph model, from which the pipeline placement is reduced to an optimisation problem (for example ILP). However, this approach produces only a unique solution, and makes it difficult to add additional constraints on the resulting pipeline.We propose to use a Timed Petri Net extension with cost, where time captures the propagation delay and cost measures the size of pipeline registers. The state space of the model captures exactly the circuit states and the branching points, so its exploration can be guided by comparing the circuit states regarding any feature (number and size of registers, critical path, throughput, etc). The pipeline exploration can be reduced to a weighted branching-time logic model-checking problem, that we prove to be PSPACEcomplete on this model.We have implemented this exploration algorithm in a prototype tool. We apply it on some arithmetic operators provided by FloPoCo showing improvements up to 35% compared to the current implementation.

Design and verification of pipelined circuits with Timed Petri Nets

“…The last pass (in green in the gure) is the one that is presented in this article and is a synthesis and extension of the articles [18,19], which introduce the model Timed Petri Net with reset and delayable transitions (RTPN in short) and present its usage for pipeline synthesis. Here, the focus is on the addition of temporal logic constraints to the generation of pipelines.…”

“…Thanks to this accurate model of pipelined synchronous circuits, we present in the Section 4 a design space exploration guided by a cost which stands for the number of needed registers (proposed in [18]). We extend this approach in the Section 5 in order to build optimized pipelines (in terms of number of registers), while guaranteeing that a set of properties are veried by the synthesized circuit.…”

“…To avoid the combinatorial explosion, the two heuristics proposed in [18] lead to good pratical results by limiting the number of delayable transitions 1 and increasing the lower bound of the reset interval.…”

“…On this example, a classical greedy as-soon-as-possible algorithm as implemented in FloPoCo [11] (a generator of pipelined arithmetic operators for FPGA), produces the example of Figure 7a, with a total of 94 ip-ops (54% more). The improvement of this approach over the classical greedy has been studied in [18], on several arithmetic circuits.…”