2006
DOI: 10.1007/11894063_7
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Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations

Abstract: Abstract. This article starts with a discussion of three different attacks on masked AES hardware implementations. This discussion leads to the conclusion that glitches in masked circuits pose the biggest threat to masked hardware implementations in practice. Motivated by this fact, we pinpointed which parts of masked AES S-boxes cause the glitches that lead to side-channel leakage. The analysis reveals that these glitches are caused by the switching characteristics of XOR gates in masked multipliers. Masked m… Show more

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Cited by 84 publications
(58 citation statements)
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“…It is known that glitches can defeat masking schemes [30,29,31]. Some masking schemes which somehow tolerate [21,36,40,22] or avoid glitches [28,32] have been put forward.…”
Section: (B))mentioning
confidence: 99%
“…It is known that glitches can defeat masking schemes [30,29,31]. Some masking schemes which somehow tolerate [21,36,40,22] or avoid glitches [28,32] have been put forward.…”
Section: (B))mentioning
confidence: 99%
“…Another well known illustration of the default of the probing security model has been given in [MPG05,MS06] where it is shown that glitches 5 enable successful attacks against theoretically sound masked implementations due to unsatisfactory leakage modeling. In a series of works, the concept of Threshold Implementations (TI) has been introduced (see e.g.…”
Section: Algorithm 16 Twomatrixquadraticmentioning
confidence: 99%
“…The application of this work to the AES SBox led the authors of [GPS14] to describe a scheme which can be secure at any order n and is a valuable alternative to the scheme proposed in [RP10]. In parallel, some schemes [BGN + 14, NRS11, PR11] have been proposed which remain secure in the probing model even in presence of so-called glitches [MS06] and the recent work [RBN + 15] has investigated relations between these schemes and the ISW construction.…”
Section: Introductionmentioning
confidence: 99%
“…The energy consumption E g ((a, b),(x, y)) has to be substituted by the expected value [17] pin-pointed that the XOR gates in masked gates are responsible for the correlation between power consumption and the value of q. In the common mask multiplier (Fig.…”
Section: Masking On Gate Level As Countermeasurementioning
confidence: 99%
“…A detailed theoretical analysis and some practical experimental results on DPA attacks by Mangard et al [16], reported that all proposed masked gates are vulnerable to powerbased side-channel leakage in the presence of glitches. This publication and there after [17] shows that the AES implementation based on masked gates are not without threats. The first successful masked AES S-box was broken by Mangard et al [5].…”
mentioning
confidence: 93%