Pinpoint pick-up and bubble-free assembly of 2D materials using PDMS/PMMA polymers with lens shapes

Toyoda, Satoshi; Uwanno, Teerayut; Taniguchi, Takashi; Nagashio, Kosuke

doi:10.7567/1882-0786/ab176b

Cited by 36 publications

(50 citation statements)

References 29 publications

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“…The optical image is also shown in Figure b. The details of the transfer process with negligible bubbles is explained in Figure S1 (Supporting Information) . The utilization of back‐gate graphite can help with increasing C ox (0.23 µF cm −2 with dielectric constant of 2.5 for h ‐BN) comparable to that for the high‐ k top gate by reducing the h ‐BN thickness to 9.5 nm, since the atomically flat surface of h ‐BN is guaranteed by the total thickness of graphite and h ‐BN (> 20 nm) (Figure S1, Supporting Information).…”

Section: Resultsmentioning

confidence: 99%

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS₂ Field‐Effect Transistors

Fang

Toyoda

Taniguchi

et al. 2019

Adv Funct Materials

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2D materials are promising to overcome the scaling limit of Si field-effect transistors (FETs). However, the insulator/2D channel interface severely degrades the performance of 2D FETs, and the origin of the degradation remains largely unexplored. Here, the full energy spectra of the interface state densities (D it ) are presented for both n-and p-MoS 2 FETs, based on the comprehensive and systematic studies, i.e., full rage of channel thickness and various gate stack structures with h-BN as well as high-k oxides. For n-MoS 2 , D it around the mid-gap is drastically reduced to 5 × 10 11 cm −2 eV −1 for the heterostructure FET with h-BN from 5 × 10 12 cm −2 eV −1 for the high-k top-gate. On the other hand, D it remains high, ≈10 13 cm −2 eV −1 , even for the heterostructure FET for p-MoS 2 . The systematic study elucidates that the strain induced externally through the substrate surface roughness and high-k deposition process is the origin for the interface degradation on conduction band side, while sulfur-vacancy-induced defect states dominate the interface degradation on valance band side. The present understanding of the interface properties provides the key to further improving the performance of 2D FETs.

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Section: Resultsmentioning

confidence: 99%

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS₂ Field‐Effect Transistors

Fang

Toyoda

Taniguchi

et al. 2019

Adv Funct Materials

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“…In addition, with unidirectional sweeping on an inclined substrate using a convex double lens PDMS/PMMA structure, the bubbles can also be squeezed out of interfaces during the pick‐up process. [ 63 ] Because the bottom flakes are verified to be torn along the edges of the top h‐BN flakes, the size of the heterostructures is limited by that of the h‐BN flakes. This limitation, in turn, provides a means of rotational stacking, which will be covered in detail in the next section.…”

Section: D Materials Assemblymentioning

confidence: 99%

“…For the PDMS carrier, [ 57,58,65d ] because the stamp is rate‐sensitive, the top material can be released with a sufficiently low peel velocity (1 mm s −1 or slower). Unlike normal polymer membranes, when the polymer carrier [ 56d,62–64,72 ] is heated above a certain temperature, a transition between the glassy state and the liquid state occurs, resulting in the release of the support material. In addition, the thermal decomposition temperatures of polymer carriers are lower than the thermal stability temperatures of most 2D materials.…”

Section: D Materials Assemblymentioning

confidence: 99%

“…Herein, the key is the utilization of the higher diffusivity [ 62b ] of the interlayer contaminants at 110°C and the unidirectional sweep force during stacking using an inclined carrier [ 62a ] or substrate. [ 63 ] More recently, advanced manipulation of 2D materials using a micro‐dome polymer has been realized. Taking advantage of the sharp edge of 2D flakes adhered to the microdome polymer, bubbles trapped in interfaces can be pushed out (Figure 15d).…”

Section: D Materials Assemblymentioning

confidence: 99%

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Stacking of 2D Materials

Guo

Zhen

Liu

et al. 2020

Adv Funct Materials

167

133

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2D layered materials have sparked great interest from the perspective of basic physics and applied science in the past few years. Extraordinarily, many novel stacked structures that bring versatile properties and applications can be artificially assembled, as exemplified by vertical van der Waals (vdW) heterostructures, twisted multilayer 2D materials, hybrid dimensional structures, etc. Compared with the ordinary synthesis process, the stacking technique is a powerful strategy to achieve high‐quality and freely controlled 2D material stacked structures with atomic accuracy. This review highlights the most advanced stacking techniques involving the preparation, transfer, and stacking of high‐quality single crystal 2D materials. Apart from the 2D–2D stacked structures, 2D–0D, 2D–1D, and 2D–3D structures offer a prospective platform for the increasing application of 2D materials. The assembly strategy and physical properties of these stacked structures strongly depend on the factors in the stacking process, including the surface quality, angle control, and sample size. In addition, comparative analysis tables on the techniques involved are also available. The summary of these strategies and techniques will hopefully provide a valuable reference for relevant work.

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“…[ 30 ] These 2D materials are stacked sequentially by a dry transfer system [ 31 ] with the help of an aluminum slope to suppress bubble formation at the 2D heterointerface, as explained in Figure S1, Supporting Information. [ 32 ] The atomic force microscope (AFM) image and Raman spectra of typical MoTe 2 / h ‐BN/graphite hetero‐stack based memory device are shown in Figures S2 and S3, Supporting Information, respectively. In most previous studies, since source and drain metal electrodes overlapped the FG through the tunnel barrier, two different tunneling paths, that is, channel to FG and metal to FG should be considered.…”

Section: Figurementioning

confidence: 99%

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

Sasaki

Ueno

Taniguchi

et al. 2020

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In recent years, 2D materials including semimetallic graphene, semiconducting transition metal dichalcogenides (TMDs) and insulating h-BN have emerged as potential next generation electronic materials. For instance, semiconducting TMDs have been studied as channels in field effect transistors The memory window of floating gate (FG) type non-volatile memory (NVM) devices is a fundamental figure of merit used not only to evaluate the performance, such as retention and endurance, but also to discuss the feasibility of advanced functional memory devices. However, the memory window of 2D materials based NVM devices is historically determined from round sweep transfer curves, while that of conventional Si NVM devices is determined from high and low threshold voltages (V th s), which are measured by single sweep transfer curves. Here, it is elucidated that the memory window of 2D NVM devices determined from round sweep transfer curves is overestimated compared with that determined from single sweep transfer curves. The floating gate voltage measurement proposed in this study clarifies that the V th s in round sweep are controlled not only by the number of charges stored in floating gate but also by capacitive coupling between floating gate and back gate. The present finding on the overestimation of memory window enables to appropriately evaluate the potential of 2D NVM devices. (FETs), since their atomically thin nature can suppress the short channel effects that scaled Si-FETs have faced. [1-3] Not only n-MoS 2 FETs [4,5] but also ambipolar WSe 2 or MoTe 2 FETs [6-8] have been widely investigated from the context of channel mobility, contact engineering, etc. In addition, to explore their intrinsic properties due to the dangling bond free interface, 2D hetero-stack technology enables the fabrication of more advanced device structure [9] where insulating h-BN is applied as the atomically flat substrate [10,11] and gate insulator [12,13] with SiO 2 compatible permittivity (2-4). [14] As well as FETs, 2D materials have been utilized in non-volatile memory (NVM) devices, which are one of key building blocks for modern integrated circuits. [15,16] In particular, lots of efforts have been devoted to floating gate (FG) type memory devices. Their device structures have also evolved from the early stage of MoS 2 channel/HfO 2 tunnel barrier/multilayer graphene FG [17] stacks to recent 2D hetero-stack of WS 2 channel/h-BN tunnel barrier/graphite FG, [18] where the large memory window over 20 V for gate voltage (V G) range of ± 25 V and a good retention characteristic of 13% charge loss after 10 years have been demonstrated. Interestingly, many other 2D NVM devices, such as black phosphorus channel device and so on, [19-22] have also exhibited the large memory window, regardless of material systems, even though the origin has rarely been discussed. Moreover, 2D hetero-stacks have recently been further extended to artificial synaptic emulators for neuromorphic computing. [23] As mentioned above, the memory window, which is defined...

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Pinpoint pick-up and bubble-free assembly of 2D materials using PDMS/PMMA polymers with lens shapes

Cited by 36 publications

References 29 publications

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS₂ Field‐Effect Transistors

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS₂ Field‐Effect Transistors

Stacking of 2D Materials

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

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Pinpoint pick-up and bubble-free assembly of 2D materials using PDMS/PMMA polymers with lens shapes

Cited by 36 publications

References 29 publications

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS2 Field‐Effect Transistors

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS2 Field‐Effect Transistors

Stacking of 2D Materials

Understanding the Memory Window Overestimation of 2D Materials Based Floating Gate Type Memory Devices by Measuring Floating Gate Voltage

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Product

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Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS₂ Field‐Effect Transistors

Full Energy Spectra of Interface State Densities for n‐ and p‐type MoS₂ Field‐Effect Transistors