$\pi$ -SCR Device for Broadband ESD Protection in Low-Voltage CMOS Technology

Lin, Chun Yu; Lai, Yu-Hsuan

doi:10.1109/ted.2019.2926813

Cited by 10 publications

(9 citation statements)

References 13 publications

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“…Two inductors were utilized in [11] to distribute the capacitances for broadband impedance match. A π-diode circuit was also employed to extend the bandwidth using a single inductor [12]. Note that the large T-coil or inductors in the previous works were placed outside of the pads, which greatly increases total chip area.…”

Section: Measurementmentioning

confidence: 99%

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Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor

et al. 2023

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In this paper, a compact and broadband electrostatic discharge (ESD) protection input/output (I/O) pad for high-speed interfaces is designed and miniaturized using a pad-stacked inductor in a 28-nm CMOS technology. A π-diode with a single inductor is adopted to compensate for the parasitic capacitance and extend the bandwidth of ESD-protected I/O pad. To minimize the increase of the chip area by the inductor, the pad-stacked inductor is proposed, where the inductor is placed below I/O pad. The eddy current, then, is induced in the I/O pad by time-varying magnetic field by the inductor, degrading the performance of the inductor, such as the reduced inductance, increased resistance and capacitance. These effects are thoroughly investigated using the developed equivalent circuit model which is also utilized to design the pad-stacked inductor. The compact and broadband π-diode with the reduced eddy current is then designed by the proper selection of the inductor layer and a patterned I/O pad. Measurement of the designed π-diode with the pad-stacked inductor exhibits broadband impedance match and insertion loss, that is, a return loss better than 10 dB up to 26.5 GHz and a 3-dB bandwidth as large as 22.9 GHz. The chip area of the π-diode remains the same as that of the I/O pad thanks to the proposed pad-stacked inductor. Therefore, the designed π-diode can be applied for the compact high-speed I/O interface circuits.INDEX TERMS Broadband, electrostatic discharge, high-speed, input/output pad.

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Section: Measurementmentioning

confidence: 99%

“…A π-diode with an inductor between two ESD diodes is another bandwidth extension technique allowing a broadband performance [12], [13]. The 1 st ESD protection diode connected to I/O pad immediately discharges the ESD current which lowers R ON [11].…”

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confidence: 99%

Compact and Broadband ESD Protection I/O Pad Using Pad-Stacked Inductor

et al. 2023

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“…Increasing the holding voltage of SCR structures through structural modification has been a hot topic in ESD research [21][22][23][24] and there are generally three methods. Firstly, the holding voltage can be increased by directly lengthening the dimension between the anode and the cathode of the device, that is, lengthening the ESD current path.…”

Section: Introductionmentioning

confidence: 99%

Analysis of current aggregation in gate-control dual direction silicon controlled rectifier

Zhong

Wang

Jin

et al. 2021

IEICE Electron. Express

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The current aggregation mechanism created by the gate structure is proposed for electrostatic discharging (ESD). Through device simulation, the size-expanded gate structure in gate-control dual-direction silicon controlled rectifier (GC-DDSCR) is found to aggregate the surface parasitic current path and the main SCR current path. The SCR current path is consequently twisted and extended to increase the holding voltage (Vh). Two GC-DDSCRs are fabricated in a 0.5μm CMOS technology and tested by transmission line pulse (TLP). The Vh increases from 13.84V to 16.44V as the gate size expands from 2.5μm to 4.5μm. The mechanism of current aggregation is verified.

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“…Guan et al used a nested structure to significantly improve the SCR holding voltage and achieve high ESD robustness [10]. Many researchers have proposed other methods to improve the ESD characteristics of SCR devices [11][12][13][14][15][16][17][18][19]. And it is commonly accepted that the conduction path of the device directly affects the SCR test indicators.…”

Section: Introductionmentioning

confidence: 99%