2017
DOI: 10.1109/taes.2017.2684998
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PI and PWM Sliding Mode Control of POESLL Converter

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Cited by 26 publications
(9 citation statements)
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“…The efficacy of the delineated sliding mode control scheme in Figure 8 is experimentally validated on a 48-to-12 V, 25 W test circuit under CCM operation. CLSDC's rated duty ratio of 54% is computed from Equation 3, and the requisite L-C elements are designed using Equation 8 for: rip c ≤ 30% and On the basis of the steps provided in the previous section, SMC gains of K p = 0.004 and K i = 2.7 × 10 4 are set to fulfill standard transient requirements 30,32,34 like start-up/disturbance settling time (T set ) ≤ 10 ms, maximum peak overshoot (M p ) ≤ 20%, widely followed in switched-mode power supplies (SMPS). Table 5 represents CLSDC specifications and components used to build the prototype circuit.…”
Section: Selection Of Circuits Components and Controller Gainsmentioning
confidence: 99%
See 3 more Smart Citations
“…The efficacy of the delineated sliding mode control scheme in Figure 8 is experimentally validated on a 48-to-12 V, 25 W test circuit under CCM operation. CLSDC's rated duty ratio of 54% is computed from Equation 3, and the requisite L-C elements are designed using Equation 8 for: rip c ≤ 30% and On the basis of the steps provided in the previous section, SMC gains of K p = 0.004 and K i = 2.7 × 10 4 are set to fulfill standard transient requirements 30,32,34 like start-up/disturbance settling time (T set ) ≤ 10 ms, maximum peak overshoot (M p ) ≤ 20%, widely followed in switched-mode power supplies (SMPS). Table 5 represents CLSDC specifications and components used to build the prototype circuit.…”
Section: Selection Of Circuits Components and Controller Gainsmentioning
confidence: 99%
“…By due fulfillment of Table 3 voltage and current stress expressions, switching devices selected in the prototype development include IRFP260N power MOSFET as switch (S) and NTSV30100S Schottky diode as D 1 , D 2 , D 3 , D 4 , and D 5 . On the basis of the steps provided in the previous section, SMC gains of K p = 0.004 and K i = 2.7 × 10 4 are set to fulfill standard transient requirements 30,32,34 like start‐up/disturbance settling time (T set ) ≤ 10 ms, maximum peak overshoot (M p ) ≤ 20%, widely followed in switched‐mode power supplies (SMPS). Table 5 represents CLSDC specifications and components used to build the prototype circuit.…”
Section: Selection Of Circuits Components and Controller Gainsmentioning
confidence: 99%
See 2 more Smart Citations
“…The drawback of this technique is that it sacrifices the disturbance rejection performance in this boundary layer. The fixed switching frequency using PWM is also reported in [38][39][40][41][42][43][44][45]. However, in this work the ideal equivalent control signal, computed from the measured system states, is PWM modulated.…”
Section: Introductionmentioning
confidence: 99%