Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

Safa, Samia; Noor, Samantha Lubaba; Khan, Zahid Hussain

doi:10.1109/ted.2017.2662580

Cited by 23 publications

(3 citation statements)

References 34 publications

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“…Comparison of performance of 45 nm CMOS with the state-of-the-art TFETs (Kumar et al , 2017; Safa et al , 2017; Luong et al , 2016; Vidhyadharan et al , 2019)…”

Section: Figurementioning

confidence: 99%

“…TFETs have significantly lower SS (20–30 mV/dec) allowing for a lower threshold voltage, (hence lower power supply voltage, V DD ). Figure 3 compares the performance of few state-of-the-art TFETs reported in literature, namely, dual metal double gate (DMDG) TFET (Kumar et al , 2017), triple metal double gate (TMDG) TFET (Safa et al , 2017), gate all around (GAA) TFET (Luong et al , 2016), gate-overlap TFET (Vidhyadharan et al , 2019) with conventional 45 nm MOSFETs.…”

Section: Introduction To Tunnel Field Effect Transistorsmentioning

confidence: 99%

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Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Vidhyadharan¹,

Vidhyadharan²

2021

WJE

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Purpose Tunnel field effect transistors (TFETs) have significantly steeper sub-threshold slope (24–30 mv/decade), as compared with the conventional metal–oxide–semiconductor field-effect transistors (MOSFETs), which have a sub-threshold slope of 60 mv/decade at room temperature. The steep sub-threshold slope of TFETs enables a much faster switching, making TFETs a better option than MOSFETs for low-voltage VLSI applications. The purpose of this paper is to present a novel hetero-junction TFET-based Schmitt triggers, which outperform the conventional complementary metal oxide semiconductor (CMOS) Schmitt triggers at low power supply voltage levels. Design/methodology/approach The conventional Schmitt trigger has been implemented with both MOSFETs and HTFETs for operation at a low-voltage level of 0.4 V and a target hysteresis width of 100 mV. Simulation results have indicated that the HTFET-based Schmitt trigger not only has significantly lower delays but also consumes lesser power as compared to the CMOS-based Schmitt trigger. The limitations of the conventional Schmitt trigger design have been analysed, and improved CMOS and CMOS–HTFET hybrid Schmitt trigger designs have been presented. Findings The conventional Schmitt trigger implemented with HTFETs has 99.9% lower propagation delay (29ps) and 41.2% lesser power requirement (4.7 nW) than the analogous CMOS Schmitt trigger, which has a delay of 36 ns and consumes 8 nW of power. An improved Schmitt trigger design has been proposed which has a transistor count of only six as compared to the eight transistors required in the conventional design. The proposed improved Schmitt trigger design, when implemented with only CMOS devices enable a reduction of power delay product (PDP) by 98.4% with respect to the CMOS conventional Schmitt trigger design. The proposed CMOS–HTFET hybrid Schmitt trigger further helps in decreasing the delay of the improved CMOS-only Schmitt trigger by 70% and PDP by 21%. Originality/value The unique advantage of very steep sub-threshold slope of HTFETs has been used to improve the performance of the conventional Schmitt trigger circuit. Novel CMOS-only and CMOS–HTFET hybrid improved Schmitt trigger designs have been proposed which requires lesser number of transistors (saving 70% chip area) for implementation and has significantly lower delays and power requirement than the conventional designs.

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“…Comparison of performance of 45 nm CMOS with the state-of-the-art TFETs (Kumar et al , 2017; Safa et al , 2017; Luong et al , 2016; Vidhyadharan et al , 2019)…”

Section: Figurementioning

confidence: 99%

Section: Introduction To Tunnel Field Effect Transistorsmentioning

confidence: 99%

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Vidhyadharan¹,

Vidhyadharan²

2021

WJE

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“…Literature also suggests that TFET devices can be used in designing reliable and low power applications like SRAM, DRAM and inverter circuit [24][25][26]. Unlike MOSFETs, TFETs exhibit unidirectional conduction because of their asymmetric source and drain architecture [24,27]. This unidirectional behaviour causes a lot of challenges for the circuit designers to design area efficient high-performance circuits.…”

Section: Rf and Analog Performance Analysismentioning

confidence: 99%

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

Dutta

Soni

Pattanaik

2018

IJET

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This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average subthreshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

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Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance

Hariprasad

Dan

Yadav

et al. 2021

Circuit Theory & Apps

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SummaryThis paper presents a double‐gate line‐tunneling field‐effect transistor (DGLTFET) device optimized for superior analog performance. DGLTFET has thrice the on currents Ion, at least one order lower off currents I o f f, twice the transconductance gm, at least two orders higher output resistance ro, and at least two orders higher overall intrinsic gain gmro than the equivalent metal‐oxide‐semiconductor field‐effect transistor (MOSFET) having the same width at the same technology node. The proposed device, being a double‐gate (DG) structure, exhibits extremely high vertical fields which ensures that line‐tunneling dominates over the point‐tunneling by several orders. This eliminates the notorious “hump” or the “kink” effects observed in conventional LTFET characteristics, which are detrimental for analog applications. In this work, we have optimized the DGLTFET device by changing critical parameters like the epi‐layer thickness and its doping concentration, which have serious influence on the line‐tunneling behavior. Optimization of the critical parameters for enhanced line‐tunneling leads to improved analog performance parameters like gm and ro, and finally, superior analog circuits. The performance of the DGLTFET was benchmarked with the equivalent MOSFET in fundamental analog VLSI circuits, namely, CS amplifier (both resistive and cascode loads), current mirror (both single‐stage and cascode configurations), and a two‐stage op‐amp. This paper shows that the DGLTFET CS amplifier has a gain‐BW product or unity‐gain BW fT of 15 GHz, while that of MOSFET CS amplifier with the same bias current is 10 GHz. The DGLTFET current mirror has at least three orders of magnitude higher ro than the corresponding MOSFET current mirror. Similarly, the common‐mode rejection ratio (CMRR) of the DGLTFET op‐amp is 57 dB compared to the CMRR of 33.5 dB of the equivalent design in standard 45‐nm complementary metal‐oxide semiconductor (CMOS) technology. The 45‐nm library is the lowest industry‐standard technology node currently available free for academic licenses in the public domain; hence, the benchmarking for validation was carried out at 45 nm. However, the claims/investigations made in this work are also valid for lower technologies, and related results are excluded in this report keeping the manuscript length in mind.

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Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

Cited by 23 publications

References 34 publications

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Improved hetero-junction TFET-based Schmitt trigger designs for ultra-low-voltage VLSI applications

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

Double‐gate line‐tunneling field‐effect transistor devices for superior analog performance

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