Physics and Design of Nanoscale Field Effect Diodes for Memory and ESD Protection Applications

Luryi, Serge; Xu, Jimmy; Zaslavsky, Alexander

doi:10.1002/9781118678107.ch4

Cited by 1 publication

(1 citation statement)

References 14 publications

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“…This phenomenon contributes to reducing power dissipation in the S-FED-based circuits. On the other hand, each M-FED used in digital VLSI designs can act as an nMOS or an pMOS; while, a pair of identical S-FEDs with the same geometries can be used in both pull-up and pull-down networks to design robust dynamic logic gates [36,39], memory cells [37,40], multiplexers [41], and electrostatic discharge protection components [42,43]. These CMOS-like configurations not only enjoy enhanced noise margin and reduced power dissipation but also suppress the area overhead taking the same width-to-length ratio into account in all S-FEDs.…”

Section: Introductionmentioning

confidence: 99%

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

GolshanBafghi

2023

JCHAR

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Nanostructured solid-state devices demonstrate prominent electronic transport properties and thus represent powerful building blocks for a wide range of analog and digital integrated circuits and systems. In this study, the integration of the side-contacted field effect diode (S-FED) with the silicon nanowire concept is pursued to create a device that maintains a substantial aspect ratio while delivering suitable execution. The nanowire side-contacted FED (NW-SFED), referred to as this apparatus, exhibits the capability to achieve an exceptionally high ON/OFF current ratio of 4×10 8 , allowing for efficient switching between ON and OFF states. While the downscaling of the planar CMOS technology has faced severe constraints, this characteristic is featured as a figure of merit for the NW-SFED device. Accordingly, the device can also be used in a coordinated device-circuit co-design framework as a promising candidate to mitigate noise, delay, and energy. Herein, a quantitative evaluation of NW-SFED's performance is conducted utilizing a semiconductor drift-diffusion solver to explore how variations in channel length, device width, as well as the dimensions of the n + and p + doped regions in the source and drain, respectively, influence its operational characteristics. The impact of the channel length, spacer length and device width on NW-SFED fabrication turned out to be negligible. In contrast, the thickness of doped regions emerged as the critical parameter in the fabrication process.

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Section: Introductionmentioning

confidence: 99%

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

GolshanBafghi

2023

JCHAR

View full text Add to dashboard Cite

show abstract

Physics and Design of Nanoscale Field Effect Diodes for Memory and ESD Protection Applications

Cited by 1 publication

References 14 publications

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

Performance and Geometry Study of Silicon Nanowire-based Field Effect Diodes (FED)

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