Physics & Modeling of Ambipolar Snapback Behavior in Gate Grounded NMOS

Micro-features of ambipolar snapback behaviour under high current injection to design capacitorless memory device

“…Keeping the same gate length and varying the contact spacing of between top body and source contact [39], we see that due to reduction in spacing, the snapback point shifts at higher drain voltage without affecting the sense margin i.e., no effect in retention time, but it will affect the response time of the memory as it is observed at the higher drain voltage. Therefore, a trade-off is maintained between performance, power dissipation, and cell area in this work.…”

“…The write '0' and write '1' were observed between 0.1V-2.25V and 3.25V-4V respectively, and the read operation was performed at 2.27V under applied zero gate bias as shown in figure 3. When we compare the bottom and side body sense window, we observe deeper snapback in the bottom body at lower voltage and allowing more voltage approximately ΔV = 2.5 V for sensing at a reduced margin of current for the same technology [39]. The cell operation in the proposed device is performed at little higher voltages compared to the scaled cells by paying the price for better sense margin allowing more current, retention time and, also the lower power dissipation due to the higher threshold voltage of the advanced cell.…”

“…Figure 5 for side body contact without LDD and our previously published paper [39] for side and bottom both shows the current-voltage characteristics under different gate lengths. Generally, structures with LDD require more voltage to trigger snapback and this will increase the series drain/source resistance.…”

“…From the figure 3, one can observe that the cell margin is about 1V and the current margin between read '0' and read '1' is shown as ΔI for 180 nm gate length top body contact structure. The margin will be less in the case of top body contact structure (figure 3), whereas higher cell margin (about 2V) is observed in the bottom body structure having the same gate length [39]. Margin and tolerance of different levels and process depend on the type of structure and the parametric variations.…”

“…The process variation for two structures (Bottom body with LDD (Lightly Doped Drain) and side body without LDD) has been shown in our previously published paper [39], and we have used the same structures again for this particular research extending our memory cell concept utilising the snapback. In that work, we have varied the gate length and the contact spacing between top body contact and source.…”