Physical Scaling Limits of FinFET Structure: A Simulation Study

Abstract

In this work an attempt has been made to analyze the scaling limits of Double Gate (DG) underlap and Triple Gate (TG) overlap FinFET structure using 2D and 3D computer simulations respectively. To analyze the scaling limits of FinFET structure, simulations are performed using three variables: finthickness, fin-height and gate-length. From 2D simulation of DG FinFET, it is found that the gate-length (L) and fin-thickness (T fin) ratio plays a key role while deciding the performance of the device. Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) increase abruptly when (L/T fin) ratio goes below 1.5. So, there will be a trade-off in between SCEs and on-current of the device since on-off current ratio is found to be high at small dimensions. From 3D simulation study on TG FinFET, It is found that both fin-thickness (T fin) and fin-height (H fin) can control the SCEs. However, T fin is found to be more dominant parameter than H fin while deciding the SCEs. DIBL and SS increase as (L eff /T fin) ratio decreases. The (L eff /T fin) ratio can be reduced below 1.5 unlike DG FinFET for the same SCEs. However, as this ratio approaches to 1, the SCEs can go beyond acceptable limits for TG FinFET structure. The relative ratio of H fin and T fin should be maximum at a given T fin and L eff to get maximum on-current per unit width. However, increasing H fin degrades the fin stability and degrades SCEs.

Optimizing Current Characteristics of 32 nm FinFET by Controlling Fin Width

“…Scaling limit is ratio of gate-length (L g ) to the fin width (W fin ). DIBL and sub threshold swing (SS) rises unexpectedly when the L g /W fin ratio drops below 1.5 [11]. For gate length L g =32 nm, determined scaling limit ratio for different fin widths of 5, 10, 20, 30, 40, and 50 nm are 6.4, 3.2, 1.6, 1.06, 0.8, and 0.6 respectively.…”

“…Hence drain electric field reduces the barrier of channel. When the drain and source proximity is consistent, then control of gate over channel region deteriorates with increased in channel volume which aftereffects in high sub-threshold swing with fin thickness [11].…”

“…Scaling ratio is decisive factor that determines the short channel effects that further defines scaling capabilities. Expansion of fin width also leads to lower the threshold voltage of the device as gate to surface potential coupling rises with fin thickness [11]. The surface potential not only based on capacitive coupling between the gate and the channel region but also on the capacitance of source/fin and drain/fin junction for shorter channel lengths.…”

Design and Performance Comparison of 6-T SRAM Cell in 32nm CMOS, FinFET and CNTFET Technologies

“…The physical and electrical characteristics of the FinFETs are presented in this section [3], [11]. The FinFETs used in this paper have a symmetrical structure, as shown in Fig.…”

High Fin Width Mosfet Using Gaa Structure

“…The important aspects of different FinFET structures are better subthreshold swing (SS) and drain-induced barrier lowing (DIBL) which is possible with optimum ratio of gate length to Fin width [6][7]. It has been widely known that the Fin width in DG MOSFETs should be less than 0.7 times the gate length for proper suppression of short-channel effects [8]. Therefore, the dimension in devices is determined by the fin width mainly and not by the gate length.…”