Physical modeling of electrical and dielectric properties of high-k ta2o5 based MOS capacitors on silicon

Abstract

In this paper we present an integral physical model for describing electrical and dielectric properties of MOS structures containing dielectric stack composed of a high-k dielectric (with emphasize on pure and doped Ta2O5) and an interfacial silicon dioxide or silicon oxynitride layer. Based on the model, an equivalent circuit of the structure is proposed. Validity of the model was demonstrated for structures containing different metal gates (Al, Au, Pt, W, TiN, Mo) and different Ta2O5 based high-k dielectrics, grown of bare or nitrided silicon substrates. The model describes very well the I-V characteristics of the considered structures, as well as frequency dependence of the capacitance in accumulation. Stress-induced leakage currents are also effectively analyzed by the use of the model.

Analysis of Conduction and Charging Mechanisms in Atomic Layer Deposited Multilayered HfO2/Al2O3 Stacks for Use in Charge Trapping Flash Memories

“…Several parameters of the interfacial layer and conduction mechanisms can be extracted, by consideration of the − characteristics in the narrow voltage range where no marked degradation and charge trapping (from −3 V to +3 V) occur and applying the comprehensive model for structures containing Ta 2 O 5 developed in [17] and explained in detail [18] for structures with various high-dielectrics. The method is briefly described below.…”

“…Saturation of the current in inversion (at positive gate polarity), observed for oxide voltages higher than 1.5 V, is explained to be due to the exhaustion of minority carriers (electrons in p-type substrate) [17]. This part has a shape of a reverse biased diode characteristics and can be included in a complete model for the device using an equivalent circuit containing a diode connected in series with the structure [18]. Since the main aim of this work is to study conduction and trapping properties of a nanolaminated high-dielectric, we do not consider this part of the characteristics.…”

“…Applicability of the theory used in this work has been previously tested on many various metal-high-/SiO 2 -Si structures, which is resumed in our review paper [18]. In inversion (positive gate in the case of a p-type substrate) saturation occurs at approximately 2 V. In accumulation, the straightforward application of the theory is limited by the appearance of wear-out and charge trapping at higher voltages, depending on the interfacial layer thickness and the high-composition and quality.…”

Progress in Materials for Microelectronics and Further Challenges

“…Stress induced leakage currents have been explained by creation of conductive paths in the SiO2 interfacial layer leading to a decrease of its effective dielectric thickness [34]. Review of the results obtained using the model mentioned above are given in [35]. Band diagram used in the model is shown in Figure 5.…”

A MODEL BASED METHOD FOR COMPARING THE PROPERTIES OF SOME METAL-Ta2O5/SiO2-Si STRUCTURES

“…In [13,14] we proposed and used a comprehensive model describing the leakage currents of thus obtained Ta2O5/SiO2 stacked layers. It has been later generalized for different similar structures [15].…”