Physical model of a local threshold voltage shift in InGaZnO thin-film transistors under current stress for instability-aware circuit design

Investigating an abnormal hump phenomenon in top gate a-InGaZnO thin-film transistors due to mobile sodium diffusion

“…It completely disappeared after 10,000 s. Therefore, it was clearly found that the hump phenomenon in the a-IGZO TFTs occurred only by positive gate bias. Meanwhile, according to previous studies on reliabilities of a-IGZO TFTs, impact ionization by strong lateral electric field in drain region of a-IGZO semiconductors can cause hump 20 , 23 , 24 . The electrical reliability in terms of hump against high drain field stress in the a-IGZO TFT was then investigated by applying continuous DC stress under a drain voltage of + 25 V and a gate voltage of + 5 V (V dg = + 20 V) for 10,000 s. As shown in Fig.…”

“…Several studies have been conducted on hump due to a gate bias stress of a-IGZO TFTs 15 – 20 . Hump phenomena are known to occur when shallow donor species such as ionized vacancies, metal interstitials, and hydrogen interstitials in a-IGZO semiconductors are trapped in the channel interface or a-IGZO edge region, or when they are trapped in the back channel.…”

“…They can eventually cause changes of subthreshold slope or on-set voltage in I–V characteristics of TFTs, resulting in high-pixel defects and bad pixel-uniformity on OLED display panels. Hump phenomena reported in a-IGZO TFTs can be caused by several factors such as back-channel conduction due to migration of various ionized defects inside IGZO semiconductors, charge trapping in the edge region of IGZO active islands, and impact ionization due to a high drain current 15 – 20 . Therefore, when a hump occurs in a TFT device, it is important to analyze the cause and present a solution for this phenomenon known to deteriorate display images.…”