Physical mechanism of source and drain resistance reduction for high-performance short-channel InGaZnO thin-film transistors

Abstract

We systematically study the mechanism of source and drain parasitic resistance reduction in amorphous InGaZnO thin-film transistors. Hall measurement shows that parasitic resistance is reduced by the increase in carrier density regardless of the source and drain processes. The results of photoluminescence, high-angle annular dark field scanning transmission electron microscope (HAADF-STEM), electron energy-loss spectroscopy (EELS), and X-ray photoelectron spectroscopy (XPS) analyses indicate that the fluctuation of In concentration at the InGaZnO surface is responsible for increase in carrier density. A top-gate InGaZnO transistor fabricated with a source drain resistance reduction process shows good short-channel immunity. The short-channel InGaZnO thin-film transistor with reduced source drain resistance is promising as the high-density back-end-of-line transistor in Si LSI.

3‐Masks‐Processed Sub‐100 nm Amorphous InGaZnO Thin‐Film Transistors for Monolithic 3D Capacitor‐Less Dynamic Random Access Memories

“…In theory, the self-aligned top-gate (SATG) OS TFT has the smallest parasitic capacitance, superior downscaling capability, and minimal processing steps, and thus could be a more feasible solution for the M3D capacitor-less eDRAM. [32,33] Nonetheless, the SATG a-IGZO TFT with sub 100-nm gate length (L g ) has rarely been reported. During the channel length downscaling, the self-aligned S/D-augmented short-channel effects (SCEs) can hardly be suppressed by the insufficient gate controllability of incumbent gate insulators (GIs), such as the commercially favorable plasma-enhanced chemical vapor deposited (PECVD) silicon oxide (SiO x ).…”

Metal Reaction-Induced Bulk-Doping Effect in Forming Conductive Source-Drain Regions of Self-Aligned Top-Gate Amorphous InGaZnO Thin-Film Transistors

“…Although the BG structure, such as the back-channel-etched structure − and the etch-stop-layer structure, , has the potential advantage of low fabrication cost because there are fewer process steps, the TG structure is more suitable for applications in the advanced large-area electronics and integrated circuits. In general, the TG structure can minimize the parasitic capacitance and device footprint and enhance the device scalability if the self-aligned (SA) source-drain (SD) regions are equipped. − On the other hand, the SD resistance ( R SD ) is a key parasitic component of SATG TFTs, which has to be minimized. The R SD is mainly composed of the metal contact resistance and the series resistance in SD regions.…”

“…To date, several implementation schemes involving heavily doping the SD regions of SATG AOS TFTs have been investigated, such as plasma treatment, − hydrogen doping, , ion implantation, − and metal reaction. − Among them, plasma treatment suffers from a thermal instability issue. The hydrogen doping usually brought about a serious and uncontrollable lateral hydrogen diffusion from the SD regions into channel region.…”