Physical Implementation of Cosine Function Used in the Hamming Window

Tahir, N.; Boudraa, Malika

doi:10.1109/ccee.2018.8634527

Cited by 2 publications

(1 citation statement)

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“…The physical implementation of our circuit on FPGAs is divided into two main blocks, a CAM-based block [40] and a Horner's rule-based block (See Fig. 3).…”

Section: Physical Implementation Processmentioning

confidence: 99%

Design and Implementation of an Error‐Margin Aware Approach for Non‐Uniform Segmentation of Elementary Functions Using Degree‐N Polynomial Approximation

Tahir,

Boudraa,

Lamini

et al. 2023

IEEJ Transactions Elec Engng

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Elementary functions are widely integrated in many embedded applications such as speech recognition and signal processing. This paper deals with the issues related to the hardware implementation of those functions. Indeed, a novel efficient Error‐Margin aware Approach for non‐uniform Segmentation of Elementary Functions using degree‐N Polynomial Approximation (EMASEF‐NPA) has been proposed. The bit‐width optimization (BWO) process has been used to obtain a better representation of the approximation polynomial coefficients. The principle of content‐addressable memory (CAM) and Horner's rules have been used in the physical implementation. Functional verification, logical synthesis, and physical implementation were performed using the FPGA platform. The results obtained using EMASEF‐NPA approach show a significant reduction, up to 70%, in the number of segments compared to conventional approaches. The findings of the physical implementation show a considerable decrease in area and delay. © 2023 Institute of Electrical Engineer of Japan and Wiley Periodicals LLC.

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“…The physical implementation of our circuit on FPGAs is divided into two main blocks, a CAM-based block [40] and a Horner's rule-based block (See Fig. 3).…”

Section: Physical Implementation Processmentioning

confidence: 99%