Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing

Nikitin, Nikita; Chatterjee, Saurav; Cortadella, Jordi; Kishinevsky, Michael; Ogras, Ümit Y.

doi:10.1109/nocs.2010.22

Cited by 8 publications

(5 citation statements)

References 23 publications

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“…In our proposal, three metrics are monitored to evaluate the performance of a symbol (schedule), and they are: Makespan (M), Load Balance (B) [14] and Average Link Load (L) [15].…”

Section: Evaluation Of Schedule Solutionmentioning

confidence: 99%

A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip

Chai¹,

Li²,

Wang³

et al. 2014

JCP

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In this paper, a List Simulated Anneal (LSA) algorithm is proposed for the DAG tasks scheduling on the Network-on-chip to simultaneously optimize makespan, load balance and average link load. A task list is first created for the DAG tasks, and the task-to-processor assignment is performed using Best Fit rule. Then the generated schedule is further optimized using LSA. In LSA, the task execution order is determined by the task list, and the task mapping solution is optimized using simulated annealing. By conducting series of simulation, the performance of our proposal is validated. Comparing to the list Best Fit and list random mapping algorithm, our LSA has 9% and 25.4% shorter makespan, 31.1% and 79.4% better load balance and 18% smaller average link load.

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“…In our proposal, three metrics are monitored to evaluate the performance of a symbol (schedule), and they are: Makespan (M), Load Balance (B) [14] and Average Link Load (L) [15].…”

Section: Evaluation Of Schedule Solutionmentioning

confidence: 99%

A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip

Chai¹,

Li²,

Wang³

et al. 2014

JCP

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“…In this paper, four common metrics, namely makespan, energy [10], link load [11] and workload balance [12], are extracted from the scheduling problem on NoC, and considered as the observed metrics.…”

Section: Metricsmentioning

confidence: 99%

BCC-DPSO Algorithm for Task Scheduling on NOC

Gao¹,

Chai³

et al. 2014

IJGDC

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In this paper, a BCC-DPSO scheduling algorithm is proposed to solve multi-objective optimization problem for task scheduling on Network-on-Chip (NoC). In our proposal, the relative advantage of the solution is evaluated by calculating its efficiency using BCC model in Data Envelopment Analysis (DEA), and the referred-time method is introduced to rank the BCC-efficient solution. Moreover, a sub-swarm strategy is adopted to reduce the high computational requirement introduced by the DEA. There are four sub-swarms, each of which optimizes one of four observed metrics, namely makespan, energy, link load and workload balance. Meanwhile, the speed vector updating formulation is modified to comply with the sub-swarm strategy. By conducting comparative simulations, the results show that our proposal produces more efficient schedule solution than other multi-objective Particle Swarm Optimization (PSO).

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“…In [9,10], the authors propose VC planning methods for NoC to customize the number of VCs and show the benefit of VC customization on NoC throughput and area. The authors of [11] and [12] investigate the topological mapping of IPs onto the NoC architectures for bandwidth and communication energy savings. The authors of [13,14] propose applicationspecific routing algorithms and show the benefits of it on NoC area and power consumptions.…”

Section: Related Workmentioning

confidence: 99%

System-level buffer allocation for application specific network-on-chip with wormhole routing

Wang¹,

Li²,

Peng³

2012

IETE Tech Rev

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A novel buffer allocation algorithm that can be used to customize the router design in application-specific Network-on-Chip (NoC) is proposed. More precisely, according to the target application and the total budget of the available buffer resources, the proposed method automatically assigns the buffer size for each input port in different routers across the NoC, such that the overall performance is maximized. Indeed, the experimental results show that while the proposed method in this paper is used, significant performance improvements can be achieved compared to the state-the-of-art buffer allocation methods. It also allows our NoC to achieve the same performance level as the NoC which assigns buffer resources by using the stateof-art buffer allocation methods but using fewer buffer resources. AUTHORSJian Wang received the B.S. and M.S.

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Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing

Cited by 8 publications

References 23 publications

A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip

A List Simulated Annealing Algorithm for Task Scheduling on Network-on-Chip

BCC-DPSO Algorithm for Task Scheduling on NOC

System-level buffer allocation for application specific network-on-chip with wormhole routing

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