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The innovation of 3D FinFETs using top‐down silicon nanofins represents a significant advancement toward scaling down microchip process nodes to the cutting‐edge 3‐nm level. While bottom‐up semiconductor nanofins also hold promise as building blocks for FinFETs, their controlled growth remains challenging. Drawing inspiration from the guided roots along brick gaps, this study shows that the aligned atomic terraces on an annealed miscut LaAlO3 surface can trigger an exceptional graphoepitaxial effect, encouraging the bottom‐up vapor‐phase growth of self‐aligned nanostructures such as CdS, CdSe, ZnSe, and ZnTe. Subsequently, the resultant CdS nanofins, characterized by narrow widths of ≈20 nm and large height‐to‐width ratios exceeding 16, can be seamlessly assembled into arrayed FinFETs on the insulating LaAlO3 substrate, obviating the need for post‐growth alignment steps. Unlike most nanostructure‐based planar transistors, which often operate in depletion mode characterized by negative thresholds, these FinFETs operate in enhancement mode with positive thresholds (≈5 V), ≈10−14‐A standby currents, and ≈108 on/off current ratios. The achieved ratio surpasses the record for planar enhancement‐mode CdS transistors by 4 orders of magnitude, primarily due to the enhanced electrostatic control over the nanofins. Overall, the graphoepitaxially side‐by‐side nanofins show tremendous potential to expand the repertoire of FinFETs based on non‐silicon semiconductors.
The innovation of 3D FinFETs using top‐down silicon nanofins represents a significant advancement toward scaling down microchip process nodes to the cutting‐edge 3‐nm level. While bottom‐up semiconductor nanofins also hold promise as building blocks for FinFETs, their controlled growth remains challenging. Drawing inspiration from the guided roots along brick gaps, this study shows that the aligned atomic terraces on an annealed miscut LaAlO3 surface can trigger an exceptional graphoepitaxial effect, encouraging the bottom‐up vapor‐phase growth of self‐aligned nanostructures such as CdS, CdSe, ZnSe, and ZnTe. Subsequently, the resultant CdS nanofins, characterized by narrow widths of ≈20 nm and large height‐to‐width ratios exceeding 16, can be seamlessly assembled into arrayed FinFETs on the insulating LaAlO3 substrate, obviating the need for post‐growth alignment steps. Unlike most nanostructure‐based planar transistors, which often operate in depletion mode characterized by negative thresholds, these FinFETs operate in enhancement mode with positive thresholds (≈5 V), ≈10−14‐A standby currents, and ≈108 on/off current ratios. The achieved ratio surpasses the record for planar enhancement‐mode CdS transistors by 4 orders of magnitude, primarily due to the enhanced electrostatic control over the nanofins. Overall, the graphoepitaxially side‐by‐side nanofins show tremendous potential to expand the repertoire of FinFETs based on non‐silicon semiconductors.
As scaling down to the nanoscale, the dramatically increased morphological deviation between nanostructures becomes a major challenge in implementing large‐scale nanodevices. On the other side of the coin, the often‐undesirable rich non‐repeatable randomness introduced during nanostructure growth and subsequent device fabrication is of great value in the implementation of physically unclonable functions (PUF), a booming innovative security primitive. Herein, it is shown that the self‐oriented organic nanowires grown on a faceted surface through a vapor transport process are advanced building blocks for the implementation of two novel PUFs. An optical PUF is first demonstrated by exploiting the unclonable morphological randomness of the self‐oriented nanowires (e.g., length, thickness, density, and location), which can provide an entity‐specific primary encryption for nanowire devices. Next, these nanowires are integrated into photodetector arrays directly on their growth substrate and accordingly enable an electrical PUF based on the inherent resistance variation between detector cells. Furthermore, by combining these two PUFs, a secondary encryption with higher security is proposed for information communication. The implementation of nanowire‐based PUFs not only opens a new device direction to exploit the annoying unclonable randomness of bottom‐up nanowires, but also provides innovative label‐free security primitives for emerging nanowire‐based devices and systems.
The monolithic integration of bottom‐up nanowires into devices requires rational growth of aligned nanowires. Of the proposed aligned growth methods, few are sufficiently general to be applicable to diverse materials and substrates. In this work, oriented poly(tetrafluoroethylene) (PTFE) grooves with nanoscale depth and width are transferred onto different substrates through a simple directional mechanical friction. This friction is achieved in a few seconds by a program‐driven handwriting machine. Various organic molecules (e.g., Alq3, NiPc, CoPc, CuPc, F16CuPc) are therefore assembled into oriented crystalline nanowires on the surface of Si, Si/SiO2, and glass. The self‐alignment of these nanowires enables a scalable device fabrication directly on growth substrates, eliminating structural damage and contamination during post‐growth alignment. For example, using the aligned F16CuPc nanowires on PTFE‐coated Si/SiO2 wafers, back‐gate field‐effect phototransistors are fabricated in a scalable manner by directly depositing an array of micro‐sized electrodes. Statistical results show that these phototransistors operate in n‐type enhancement mode with thresholds of a few volts. In addition, they exhibit fast photoresponse on the order of tens of milliseconds and long‐term stability in the vis–NIR spectrum. The generality of this guided nanowire growth and resulting monolithic devices offer new opportunities for the monolithic integration of nanowire‐based devices.
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