Photoresist 3D profile related etch process simulation and its application to full chip etch compact modeling

Wu, Cheng-En; Yang, Wayne; Luan, Lan; Song, Hua

doi:10.1117/12.2086048

Cited by 8 publications

(5 citation statements)

References 1 publication

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“…The explicit consideration of the impact of ADI profile on subsequent etch bias in an OPC model was demonstrated by Wu et al with some good success. 15 Considering the ion flux at δ in Eq. 2 and Fig.…”

Section: ∫ ∫mentioning

confidence: 99%

“…Executing these kind of simulation suites 19 in-line with a simulation tasked with moving photomask edges 5,6 was clearly not practical even with some advances incorporating compact models. 15 A more modest approach was to evaluate through-pitch structures and create rules for edge placement based on insights from simulation results. A demonstration of the impact of such a rule on a through-pitch test structure is shown in Fig.…”

Section: Integration Modeling and Rule Generationmentioning

confidence: 99%

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Etch aware computational patterning in the era of atomic precision processing

Ventzek

Shinagawa

Ranjan

2019

Advanced Etch Technology for Nanopatterning VIII

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Etch processes have always involved inherent process trade-offs related to fundamental plasma parameters to achieve planar patterning metrics related to damage, aspect ratio dependences and profile. Today, we are in a new era of "area selective etch." Advanced patterning (SAXP, (LELE) n), logic, memory and interconnect applications beyond 3 nm involve, in one way or another, topographies that require etch "control" at every surface. Achieving profile specifications will require the ability to conjure isotropy control at will. Vehicles to achieving this include novel precursors and hybrid processes involving combinations of deposition and plasma etch as we know it. Ultimately, to differentiate surfaces comprising silicon, silicon oxides and nitrides, and organics require active modification at the first surface reactive monolayer to be able to differentiate them in each process step with respect to any surface normal on the wafer plane. This presentation will start with a review of today's state-of-the-art means for atomic precision processing of surfaces. A simulation science perspective to process integration modeling introduces methods for surface chemistry control that lend themselves to achieving area selective etch. In the end, surface chemistry control is not a cure-all. Finally, a combination of plasma diagnostics and simulation will be needed to assist plasma process controls for scaling at 3 nm and beyond.

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Section: ∫ ∫mentioning

confidence: 99%

Section: Integration Modeling and Rule Generationmentioning

confidence: 99%

Etch aware computational patterning in the era of atomic precision processing

Ventzek

Shinagawa

Ranjan

2019

Advanced Etch Technology for Nanopatterning VIII

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“…Several proprietary and open-source simulation frameworks with the capability to describe the complex processes occurring in gate stack patterning, are readily available. Some well-known frameworks and the numerical methods on which they are based, are discussed here briefly: Sentaurus Topography [78] is a commercial simulator developed by Synopsys (Mountain View, CA, USA), which uses level set based surface descriptions for topography changes, cell based representations for chemical surface reactions, and provides Monte Carlo methods for particle transport [79]. Dunn et al [80] successfully used this tool to simulate the fabrication of FinFET structures of the 7 nm node.…”

Section: Simulation Softwarementioning

confidence: 99%

“…Sentaurus Topography [78] is a commercial simulator developed by Synopsys (Mountain View, CA, USA), which uses level set based surface descriptions for topography changes, cell based representations for chemical surface reactions, and provides Monte Carlo methods for particle transport [79]. Dunn et al [80] successfully used this tool to simulate the fabrication of FinFET structures of the 7 nm node.…”

Section: Simulation Softwarementioning

confidence: 99%

Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review

2018

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Semiconductor device dimensions have been decreasing steadily over the past several decades, generating the need to overcome fundamental limitations of both the materials they are made of and the fabrication techniques used to build them. Modern metal gates are no longer a simple polysilicon layer, but rather consist of a stack of several different materials, often requiring multiple processing steps each, to obtain the characteristics needed for stable operation. In order to better understand the underlying mechanics and predict the potential of new methods and materials, technology computer aided design has become increasingly important. This review will discuss the fundamental methods, used to describe expected topology changes, and their respective benefits and limitations. In particular, common techniques used for effective modeling of the transport of molecular entities using numerical particle ray tracing in the feature scale region will be reviewed, taking into account the limitations they impose on chemical modeling. The modeling of surface chemistries and recent advances therein, which have enabled the identification of dominant etch mechanisms and the development of sophisticated chemical models, is further presented. Finally, recent advances in the modeling of gate stack pattering using advanced geometries in the feature scale are discussed, taking note of the underlying methods and their limitations, which still need to be overcome and are actively investigated.

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“…On the other hand, MB-EPC is implemented to model etch bias as a function of a few empirical parameters of a specific shape and its environment. These parameters are density kernel, blocked kernel, and visible kernel [19]- [21]. The coefficients of this polynomial function are determined empirically.…”

Section: Introductionmentioning

confidence: 99%

Intelligent Photolithography Corrections Using Dimensionality Reductions

et al. 2019

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With the shrinking of the IC technology node, optical proximity effects (OPC) and etch proximity effects (EPC) are the two major tasks in advanced photolithography patterning. Machine learning has emerged in OPC/EPC problems because conventional optical-solver-based OPC is time-consuming, and there is no physical model existing for EPC. In this work, we use dimensionality reduction (DR) algorithms to reduce the computation time of complex OPC/EPC problems while the prediction accuracy is maintained. Also, we implement a pure machine learning approach where the input masks are directly mapped to the output etched patterns. While one photolithographic mask can generate many experimental patterns at once, our pure ML-based approach can shorten the trial-and-error period in the photolithographic correction. Additionally, we demonstrate the automation in SEM images preprocessing using feature detection, and this facilitates intelligent manufacturing in semiconductor processing. The input vector dimensions are effectively reduced by two orders of magnitude while the observed mean squared error is not affected significantly. The computation runtime is reduced from 4804 s of the baseline calculation to 10 s-200 s The MSE values changed from the baseline 0.037 to 0.037 for singular value decomposition (SVD), to 0.039 for independent component analysis (ICA), and to 0.035 for factor analysis (FA).

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Photoresist 3D profile related etch process simulation and its application to full chip etch compact modeling

Cited by 8 publications

References 1 publication

Etch aware computational patterning in the era of atomic precision processing

Etch aware computational patterning in the era of atomic precision processing

Modeling of Gate Stack Patterning for Advanced Technology Nodes: A Review

Intelligent Photolithography Corrections Using Dimensionality Reductions

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