2021 IEEE 17th International Conference on Group IV Photonics (GFP) 2021
DOI: 10.1109/gfp51802.2021.9673842
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Photonic Wire Bonding for Silicon Photonics III-V Laser Integration

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Cited by 7 publications
(4 citation statements)
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“…Fabrication of the silicon photonic (SiP) chip, as well as the sample assembly and photonic wire bonding, was done inhouse. The chip was fabricated using the same in-house techniques as are used for on-chip laser integration [6], in which the SiP waveguides were patterned and etched using EBeam lithography (JEOL JBX-8100FS) and ICP-RIE etching (Oxford PlasmaPro 100 Cobra) and the cavity was patterned and etched using maskless lithography (Heidelberg MLA-150) and Bosch etching (SPTS Rapier DRIE). The SOA was attached to the cavity using a die bonder (Tresky T-3000 Pro) and indium reflow soldering.…”
Section: Fabricationmentioning
confidence: 99%
“…Fabrication of the silicon photonic (SiP) chip, as well as the sample assembly and photonic wire bonding, was done inhouse. The chip was fabricated using the same in-house techniques as are used for on-chip laser integration [6], in which the SiP waveguides were patterned and etched using EBeam lithography (JEOL JBX-8100FS) and ICP-RIE etching (Oxford PlasmaPro 100 Cobra) and the cavity was patterned and etched using maskless lithography (Heidelberg MLA-150) and Bosch etching (SPTS Rapier DRIE). The SOA was attached to the cavity using a die bonder (Tresky T-3000 Pro) and indium reflow soldering.…”
Section: Fabricationmentioning
confidence: 99%
“…Herein, we explore the use of photonic wire bonds (PWBs), which are flexible interconnections with low insertion loss for laser-to-chip and fiberto-chip integration. [22,23] They also have been applied in hybridintegrated compact optical transceivers. [24] Furthermore, PWBs have been employed to address the complex packaging requirements of neuromorphic photonic accelerator architectures.…”
Section: Introductionmentioning
confidence: 99%
“…Our proof-of-concept demonstration is implemented on a silicon-on-insulator (SOI) platform. A 15 × 15, disordered microring lattice is used to generate the speckle patterns and a photonic wire bond (PWB) is used to connect the device to a fiber [30,31]. The fiber-to-chip interconnect had a minimum insertion loss of 1.45 dB/facet and a 3-dB bandwidth larger than 300 nm.…”
Section: Introductionmentioning
confidence: 99%