Photonic networks-on-chip: Opportunities and challenges

Petracca, Michele; Bergman, Keren; Carloni, Luca P.

doi:10.1109/iscas.2008.4542036

Cited by 12 publications

(9 citation statements)

References 17 publications

(17 reference statements)

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“…The on-chip optical communication using waveguides as the transmission medium has essential advantages compared to traditional electrical communication [1][2][3][4]. The characteristics of low delay, high bandwidth, and low power consumption can effectively solve the ongoing bottlenecks of on-chip communication [5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping

Feng

2020

IEICE Electron. Express

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Wavelength division multiplexing (WDM) mesh-based optical network on chip (ONoC) have recently received considerable attention due to their regular topology and higher throughput. However, available wavelengths are finite resources. Thus, to minimize the number of wavelengths, this letter proposes an efficient WDM mesh-based ONoC mapping approach, which is based on a particle swarm optimization algorithm. Experimental results reveal that our proposal has a positive effect in minimizing the number of wavelengths needed compared to random mapping. The tradeoff between the number of wavelengths and the network size is also investigated, and it is found that increasing the network size can reduce the number of wavelengths needed. Meanwhile, the experiments show that the structure has better network performance and less communication resource utilization.

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Section: Introductionmentioning

confidence: 99%

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping

Feng

2020

IEICE Electron. Express

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“…The NoC based photonic communications support a mechanism for large data transmission with higher bandwidth and less power consumption. The photonic based NoC supports Multiple cores interface using gateway switch [1] [3]. Multiple cores residing in a single chip (MPSoC) exist towards mixed-criticality system includes dependability, security, and different block access with shared resources.…”

Section: Introductionmentioning

confidence: 99%

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

Guruprasad¹,

B.S²

2019

IJACSA

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Network on Chip (NoC) is an emerging interconnect solution with reliable and scalable features over the System on Chip (SoC) and helps to overcome the drawbacks of bus-based interconnection in SoC. The multiple cores or other networks have a boundary which is limited to communicate with devices, which are directly connected to it. To communicate with these multiple cores outside the boundary, the NOC requires the gateway functionality. In this manuscript, a cost-effective Network Gateway (NG) model is designed, and also the interconnection of a network gateway with multiple cores are connected to the NoC based system is prototyped on Artix-7 FPGA. The NG mainly consists of Serializer and deserializer for transmitting and receiving the data packets with proper synchronization, temporary register to hold the network data, electronic crossbar switch is connected with multiple cores which are controlled by switch controller. The NG with the Router and different sizes of NoC based system is designed using congestionfree adaptive-XY routing. The implementation results and performance evaluation are analyzed for NG based NoC in terms of average Latency and maximum Throughput for different Packet Injection Ratio (PIR). The proposed Network gateway achieves low latency and high throughput in NoC based systems for different PIR.

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“…Optical interconnects are key components in these new system architectures because of their bandwidth advantage over copper. Recently, silicon photonics (SiP) has drawn a lot of attention as an enabling technology for highdensity, low-power optical integration [1]. This new technology platform uses large-scale complementary metal-oxide-semiconductor (CMOS) fabrication methods to integrate functional photonic devices into silicon chips in a cost effective manner.…”

Section: Introductionmentioning

confidence: 99%

Mode size converter designs for fabrication of ultra-low loss optical interconnects

Bowen

Ling

Sun

et al. 2016

2016 Pan Pacific Microelectronics Symposium (Pan Pacific)

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Over the past decade, the silicon photonics industry has made fantastic progress in implementing a wide range of optical and electro-optical devices using infrastructure and low-cost, high-volume, manufacturing technologies from the microelectronics industry. Many technical challenges have been solved. However, ultra-low loss light coupling at the interface between a high-index, sub-micron silicon waveguide and single mode fiber (SMF) remains problematic, and has attracted world-wide efforts to propose new designs and integration processes. Two widely used strategies have been reported in the literature: out-of-plane grating couplers and in-plane edge couplers with mode size converters (MSCs). Compared with most grating couplers, mode size converters have the advantage of broader bandwidth (> 100nm) and more design freedom to achieve good light coupling efficiency. In this paper, we will focus on designs for high coupling efficiency using inverse tapered mode size converters that will adiabatically transform the small mode size of a silicon waveguide to match the large mode size of a single mode fiber. Our designs involve mode size matching by the use of vertically coupled waveguides. Large scale fabrication of mode size converters at low cost and high repeatability is desired. Mode size converters can for example, be made of silicon, silicon nitride, or polymer materials. However, mode size converters with 3D gradually tapered structures cannot be fabricated in a straightforward manner by classic CMOS manufacturing processes. In this paper, a one-step, gray scale photolithography-based high efficiency mode size converter fabrication flow will be discussed. We will apply this methodology for the design of both a silicon nitride based mode size converter and also to a polymer based mode size converter. Notably, gray scale photolithography can be readily integrated into multi-mask CMOS processes to provide one-step manufacturing for mode size converters at extremely low cost and accurate positioning.

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Photonic networks-on-chip: Opportunities and challenges

Cited by 12 publications

References 17 publications

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping

Minimizing the number of wavelengths in a cluster WDM mesh-based ONoC through application-specific mapping

Performance Evaluation of Network Gateway Design for NoC based System on FPGA Platform

Mode size converter designs for fabrication of ultra-low loss optical interconnects

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