Phoenix NoC: A distributed fault tolerant architecture

Marcon, César; Amory, Alexandre M.; Webber, Thais; Volpato, Thomas; Poehls, Leticia Bolzani

doi:10.1109/iccd.2013.6657018

Cited by 7 publications

(23 citation statements)

References 9 publications

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“…It comprises hardware part placed on each NoC router and software part (i.e. OsPhoenix) placed into the operating system of each PE [5], which is composed of a processormemory pair [4]. In addition, Phoenix NoC employs a direct 2D mesh topology consisting of routers using bidirectional links to connect with other routers and PEs.…”

Section: Phoenix Noc's Architecturementioning

confidence: 99%

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A fault prediction module for a fault tolerant NoC operation

Silveira

Bodin

Ferreira

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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Each new production technology of integrated circuit (IC) drives more transistors area reduction, implying smaller and denser circuits. This scenario allows integrating several Processing Elements (PEs) into the same IC with efficient communication architecture such as the scalable topologies of Network on Chip (NoC). However, these newer production technologies introduce more defects in various parts of the IC that have to be detected and well corrected to prevent malfunction of the IC. This work presents the Fault Prediction Module (FPM), which presents low area consumption and a power circuit based on thresholds enabling to detect link quality, i.e. operating properly, operating with fault tendency or with permanent fault. Additionally, we show how to tune the FPM threshold parameter aiming to use this circuit as a mechanism with comprehensive fault model. The set of experimental results shows the effectiveness of our proposal.

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Section: Phoenix Noc's Architecturementioning

confidence: 99%

“…The main challenge of FPM design is how the threshold parameters have to be set for the correct detection of fault tendency and permanent faults. FPM is part of the fault-tolerant mechanism of Phoenix NoC [4], and each input link of NoC's router contains a FPM.…”

Section: Introductionmentioning

confidence: 99%

A fault prediction module for a fault tolerant NoC operation

Silveira

Bodin

Ferreira

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

Self Cite

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“…Moreover, in a given set of scenarios, some ones can cover others, reducing a large set of preprocessing scenarios, which provides two new and important contributions of this work: (i) a novel way to reduce a large set of scenarios based on cross-correlation measure to identify dissimilarities in sets of irregular matrix topologies, which enables to minimize the storage area of preprocessing scenarios; and (ii) a method to identify the most similar scenarios, and, consequently, the best scenario substitution, which enables to search fast and efficient routing solutions. Figure 1 shows the Phoenix distributed fault-tolerant architecture [5] over an NoC-based MPSoC platform comprising a hardware part (i.e. HwPhoenix) placed on each router of the NoC and a software part (i.e.…”

Section: Related Work and Main Contributionsmentioning

confidence: 99%

“…Examples of control packets are (i) TEST_LINKS used to test all links of the local router; (ii) TR_ROUT_TAB, RD_ROUT_TAB and WR_ROUT_TAB used to transmit, to read and to write the Routing Table of This work aggregates to the previous Phoenix architecture [5], the follow contributions: (i) fault detection and correction modules encompassed by a Hamming Encoder (HE) and a Hamming Decoder (HD); (ii) a fault diagnosis circuit named Fault Prediction Module (FPM); and (iii) the scenarios preprocessing capability, providing fast reconfiguration and deadlock-free routing in case of fault detection.…”

Section: Phoenix's Architecturementioning

confidence: 99%

“…This paper proposes an efficient approach to deal with dynamic faults on NoC links employing Phoenix [5] as the fault-tolerant target system, which comprises a 2D mesh NoC and a layer of an Operating System. The approach consists of preprocessing fault scenarios to fast reconfigure the network with a new deadlock-free routing in case of fault detection.…”

Section: Introductionmentioning

confidence: 99%

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Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs

Silveira

Marcon

Cortez

et al. 2015

2015 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing

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Newest processes of CMOS manufacturing allow integrating billions of transistors in a single chip. This huge integration enables to perform complex circuits, which require an energy efficient communication architecture with high scalability and parallelism degree, such as a Network-on-Chip (NoC). However, these technologies are very close to physical limitations implying the susceptibility increase of faults on manufacture and at runtime. Therefore, it is essential to provide a method for efficient fault recovery, enabling the NoC operation even in the presence of faults on routers or links, and still ensure deadlock-free routing even for irregular topologies. A preprocessing approach of the most probable fault scenarios enables to anticipate the computation of deadlock-free routings, reducing the time necessary to interrupt the system operation in a fault event. This work describes a preprocessing technique of fault scenarios based on forecasting fault tendency, which employs a fault threshold circuit and a high-level software that identifies the most relevant fault scenarios. We propose methods for dissimilarity analysis of scenarios based on measurements of cross-correlation of link fault matrices. At runtime, the preprocessing technique employs analytic metrics of average distance routing and links load for fast search of sound fault scenarios. Finally, we use RTL simulation with synthetic traffic to prove the quality of our approach.

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