2011 IEEE International Parallel &Amp; Distributed Processing Symposium 2011
DOI: 10.1109/ipdps.2011.89
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PHAST: Hardware-Accelerated Shortest Path Trees

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Cited by 64 publications
(60 citation statements)
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“…However, the preprocessing of Arc-Flags is, in general, very time-consuming. In the literature, several strategies have been proposed to precompute the Arc-Flags, which we briefly describe in what follows; for more details we refer to [12,22]. AF1 [22]: a full shortest path tree rooted at each boundary node of each region is built in the reverse graph, by running Dijkstra's algorithm.…”
Section: Arc-flagsmentioning
confidence: 99%
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“…However, the preprocessing of Arc-Flags is, in general, very time-consuming. In the literature, several strategies have been proposed to precompute the Arc-Flags, which we briefly describe in what follows; for more details we refer to [12,22]. AF1 [22]: a full shortest path tree rooted at each boundary node of each region is built in the reverse graph, by running Dijkstra's algorithm.…”
Section: Arc-flagsmentioning
confidence: 99%
“…PHAST [12]: a full shortest path tree rooted at each boundary node of each region is built by running PHAST (Parallel Hardware-Accelerated Shortest path Trees), a family of algorithms proposed in [12] which take advantage of features of modern CPU architectures, such as multi-core, thus requiring a parallel setup. In [12], a sequential version of PHAST has also been proposed.…”
Section: Arc-flagsmentioning
confidence: 99%
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