Phase Noise Analysis of Clock Recovery Based on an Optoelectronic Phase-Locked Loop

Abstract

Abstract-A detailed theoretical analysis of a clock-recovery (CR) scheme based on an optoelectronic phase-locked loop is presented. The analysis emphasizes the phase noise performance, taking into account the noise of the input data signal, the local voltage-controlled oscillator (VCO), and the laser employed in the loop. The effects of loop time delay and the laser transfer function are included in the stochastic differential equations describing the system, and a detailed timing jitter analysis of this type of optoelectronic CR for high-speed optical-time-division-multiplexing systems is performed. It is shown that a large loop length results in a higher timing jitter of the recovered clock signal. The impact of the loop length on the clock signal jitter can be reduced by using a low-noise VCO and a low loop filter bandwidth. Using the model, the timing jitter of the recovered optical and electrical clock signal can be evaluated. We numerically investigate the timing jitter requirements for combined electrical/optical local oscillators, in order for the recovered clock signal to have less jitter than that of the input signal. The timing jitter requirements for the free-running laser and the VCO are more relaxed for the extracted optical clock (lasers's output) signal.Index Terms-Clock recovery (CR), optical time division multiplexing (OTDM), optoelectronic phase-locked loop (OPLL), oscillator noise, phase noise, stochastic differential equations, time delay, timing jitter.

640-Gbit/s Data Transmission and Clock Recovery Using an Ultrafast Periodically Poled Lithium Niobate Device

“…9 (top), the ERGO cuts away excess phase noise above the ERGO PLL bandwidth of 20 kHz. In the VCO SSCR, there is a peak at about 200 kHz, which stems from the PLL bandwidth of about 200 kHz, It is at this frequency that the PLL shifts from tracking the data SSCR to following the VCO SSCR [14]. This peak and the phase noise associated with it is eliminated by the ERGO.…”

“…Reducing the loop length from its present 60 m, allowing for an expansion of the PLL bandwidth, will also help to lower the timing jitter, as the influence of the low-jitter data signal in this setup will dominate [14].…”

“…4), which is expected to reduce the contrast of the error signal. The overall loop length with pigtails and EDFAs is about 60 m, and, with a PLL bandwidth of 200 kHz, the loop is expected to be stable, according to [14]. Fig.…”