Phase-locked Loop Based on Integrating Scanning Conversion

Abstract

A new principle for developing a phase-locked loop (PLL) based on integrating scan conversion is proposed. The PLL is a nonlinear pulse system based on the closed structure of an integrating scanning converter (ISC) operating in the mode of external synchronization with circuit voltage frequency. The block diagrams, the waveform diagram and frequency synchronization conditions for integrating scanning converter switch by outer signalsbipolar rectangle and harmonic, are provided. The recommendations for choosing the frequency ratio of self-oscillations of the scanning converter and circuit voltage frequency were tested. It is shown that the integrating PLL fully adapts to amplitude instability and circuit voltage frequency within the range of 50% and higher.Unlike the existing PLLs, the proposed system is a first-order adaptive filter, whose bandwidth is automatically tuned to the amplitude and frequency of circuit voltage. This property of the integrating PLL allows suppressing higher harmonics in the supply circuit with frequency instability within the range of 50% and higher. The system's high noise immunity to commutation distortions of circuit voltage is also shown. These results show the practicability of using it in semiconductor converter control systems, which receive power from an independent low-power supply system, for example, diesel or wind power generating plants. The limits of the dynamic parameters of this system for gradual change of amplitude and circuit voltage frequency have been determined. A three-phase reverse thyristor rectifier is used as an example of a crossed synchronization flow-chart. The recommendations on choosing the parameters of the integrating PLL and also the results of the practical application of the synchronizing unit as a part of semiconductor converter control systems are provided.