Phase-lock-loop A/D converter

Abstract

A HIGH ACCURACY A/D converter that can be integrated into one monolithic chip has been devised. Utilized is a VCO phaselocked to a submultiple, M, of the system clock frequency, F , to convert the input/reference voltage ratio into a variable duty cycle, D, pulse waveform. D is measured using a counter and the clock. Accuracy depends upon the ratio of two resistors and resolution upon M. The system differs from other A/D converters utilizin VCOs in that no other active analog devices are r e q~i r e d~" " '~. Figure 1 illustrates the basic system. The clock is divided by M and compared to the VCO output through an edge sensitive set-reset flipflop, FF. The output of FF has a duty cycle, D, that controls an analog switch, SI. The average feedback voltage is thus Vr,f D. This feedback voltage locks the VCO frequency to FJM. Because of the voltage divider action of R1 and Rz, the change in D with changes in Vin is: The output of F F is inverted and fed to a gate controlling clock pulses into the counter. The count, C, of the counter in any one period, M/Fc, measures 1-D with a resolution of 1/M. The change in count with input voltage is thus: Accuracy is limited only by S1, R2/R1, and VTef, while resolution is set by M. Conversion time, T,, is a function of Fc, M, and loop settling time. Assuming that the VCO has a gain of A Fc/M Hz/V and applying basic loop dynamics thenThe assumption of a VCO with a constant Hz/V conversion gain has been assumed for the basic system. A practical system must allow for drift and nonlinearity of this gain. Fortunately, small changes to the basic system can correct for these difficulties and at the same time produce a C that is a dircct reading of the normalized input voltage. Figure 2 s h o w the practical system. Compensation of VCO nonlinearity is achieved by restricting the voltage ripple at the VCO summing point; E , to a small percentage of the VCO range. Since only the linearity over this percentage range is important to measurement accuracy, reducing the ripple improves effective linearity. A lead-lag filter composed of R3 and C3 is used to reduce ripple in Figure 2. Loop settling time is lengthened so that selection of R3 and C3 is a complex tradeoff between speed, accuracy, and VCO design. Equation 3 still gives an indication of T,, but only as a rough proportionality.Operation of a single-ended V-CO results in a bias voltage at E that is a function of VCO gain and clock frequency. This bias results in an offset in C. The offset (assuming reasonable short term stability in the VCO and clock) is subject to long term variations and must be cancelled. By adding another switch, Sz, and using an UP/DOWN counter, the system will have automatic zeroing. Each measurement takes two cycles thus doubling conversion time. The first cycle is made with the counter in the DOWN mode and Sz grounded.The second cycle uses the counter in the UP mode and S2 selects Vin. Since the offset is counted down and then up it makes no contribution to the final count. Differential measurements can be mad...