PETS: Power and energy estimation tool at system-level

Rethinagiri, Santhosh-Kumar; Palomar, Oscar; Unsal, Osman S.; Cristal, Adrián; Ben-Atitallah, Rabie; Niar, Smaïl

doi:10.1109/isqed.2014.6783373

Cited by 20 publications

(14 citation statements)

References 17 publications

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“…In [15] Rethinagiri et al describes a tool for power and energy estimation at system-level. Like in [14] also this tool consists of the same two parts.…”

Section: Related Workmentioning

confidence: 99%

“…This calls for the power management technique DVFS to adjust processor's voltage plus its frequency. Both parameters are observed by our own functional test framework, but in [15] they are only configured by the executed application on the virtual platform and can only be observed indirectly through the power results. In that case, if the accuracy of the power model is not high enough or the difference in power consumption of two subsequent modes is too small, the change is not traceable.…”

Section: Related Workmentioning

confidence: 99%

“…We have decided to implement our functional test framework for power management techniques in OVP, for the following reasons: (1) OVP is commercially proven, provides a rich set of functional processor models and is one of the fastest simulators in its class; (2) As for all dynamic binary translation approaches, different target compilers can be used with all possible optimizations; (3) The target processor debugging tools can be used directly. Since the approaches presented in [12], [14], [15] also use OVP, our functional test framework can directly attached to them. But also the other functional simulation based approaches in [8], [9], [10] can benefit from our work with some effort to collect the needed values in their different simulators.…”

Section: Related Workmentioning

confidence: 99%

See 2 more Smart Citations

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

Schreiner

Fakih

Gruettner

et al. 2017

2017 Euromicro Conference on Digital System Design (DSD)

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Abstract-Today's Cyber-Physical Systems (CPS) are witnessing a growing complexity in terms of the number of components and computational power in order to meet the requirements of nowadays applications. For this reason and due to their energy efficiency, Multiprocessor system-on-chips (MPSoC) are becoming ubiquitous. Yet, since these systems are often used in batterydriven and/or small housing use cases, the correct configuration of their power management techniques is an important factor in system design and can be related to possible safety aspects of the system. This calls for an adequate test framework, which is able to observe the power management functionalities of CPS, even before the actual hardware platform is available. The use of virtual platforms for functional validation, that allows executing the CPS's real target platform compatible application binary code on a generic host computer, is currently being adopted by the industry. This work focuses on enhancing industrial OVP virtual platforms by a functional test framework of the power management techniques. We will demonstrate and evaluate how this framework maintains to observe the power management techniques of the system under test. The evaluation uses a Xilinx ZC702 board based on a Xilinx Zynq-7000 MPSoC and its correspondent virtual platform in OVP. Results show that the functional test framework is able to analyze the different modes of operation regarding the power management techniques of the Xilinx Zynq processing system.

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“…In [15] Rethinagiri et al describes a tool for power and energy estimation at system-level. Like in [14] also this tool consists of the same two parts.…”

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

Schreiner

Fakih

Gruettner

et al. 2017

2017 Euromicro Conference on Digital System Design (DSD)

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show abstract

“…To meet performance requirements and to achieve quick exploration times, the EDA industry relies on MDE approaches demanding for system power consumption estimation at early stage in the design flow. STORM [13], Gaspard2 [14] [15] , PETS [16] , CAT [17] and TTool [18] are MDE-based power-aware tools that rely on high-level models. While STORM and CAT use AADL-based design entries for system-level power and energy consumption estimation, PETS benefits from the generated SystemC code to estimate the power consumption during simulations.…”

Section: B Eda Tools For Power Estimation and Optimizationmentioning

confidence: 99%

On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC

Ammar

Baklouti

Pelcat

et al. 2016

2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)

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Abstract-Massively Parallel Multi-Processors System-onChip (MP2SoC) architectures have been widely deployed to run challenging high-performance computations. However, the ever greater demand for energy efficiency fosters energy budgeting in MP2SoC systems. Nowadays, having the appropriate Electronic Design Automation (EDA) tools for power estimation is mandatory. The major challenge for the design of such tools is to reach a better tradeoff between accuracy and time-to-market. This paper presents a Model Driven Engineering (MDE)-based energy-aware Design Space Exploration (DSE) approach allowing the designer to take the power consumption criterion into account early in the design flow. The originality of this approach is that it integrates the Energy-Aware Duplication (EAD) algorithm that strives to balance schedule lengths and energy savings by considering the most important sources of energy consumption in MP2SoC: the massive number of processing elements (PE) and the high-speed Network-on-Chip (NoC). To demonstrate the effectiveness of the proposed approach, we conducted experiments using the H.263 encoder application. The obtained results demonstrated that EAD can effectively save energy in MP2SoC systems. They also showed that our MDE approach is capable of accelerating the DSE process to make early energy-efficient design decisions.

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“…Architecture-level heterogeneity. In the context of ParaDIME, we will use the Power Estimation Tool at System-level (PETS) [6], for estimating and optimizing power. This tool simplifies application porting as well as enables the user to choose the processor architecture upon which to perform hardware/software co-simulation.…”

Section: Heterogeneous Computingmentioning

confidence: 99%

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Rethinagiri

Palomar

Sobe

et al. 2015

Microprocessors and Microsystems

Self Cite

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a b s t r a c tDramatic environmental and economic impact of the ever increasing power and energy consumption of modern computing devices in data centers is now a critical challenge. On the one hand, designers use technology scaling as one of the methods to face the phenomenon called dark silicon (only segments of a chip function concurrently due to power restrictions). On the other hand, designers use extreme-scale systems such as teradevices to meet the performance needs of their applications which in turn increases the power consumption of the platform. In order to overcome these challenges, we need novel computing paradigms that address energy efficiency. One of the promising solutions is to incorporate parallel distributed methodologies at different abstraction levels.The FP7 project ParaDIME focuses on this objective to provide different distributed methodologies (software-hardware techniques) at different abstraction levels to attack the power-wall problem. In particular, the ParaDIME framework will utilize: circuit and architecture operation below safe voltage limits for drastic energy savings, specialized energy-aware computing accelerators, heterogeneous computing, energy-aware runtime, approximate computing and power-aware message passing. The major outcome of the project will be a noval processor architecture for a heterogeneous distributed system that utilizes future device characteristics, runtime and programming model for drastic energy savings of data centers. Wherever possible, ParaDIME will adopt multidisciplinary techniques, such as hardware support for message passing, runtime energy optimization utilizing new hardware energy performance counters, use of accelerators for error recovery from sub-safe voltage operation, and approximate computing through annotated code. Furthermore, we will establish and investigate the theoretical limits of energy savings at the device, circuit, architecture, runtime and programming model levels of the computing stack, as well as quantify the actual energy savings achieved by the ParaDIME approach for the complete computing stack with the real environment.

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PETS: Power and energy estimation tool at system-level

Cited by 20 publications

References 17 publications

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual Platforms

On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

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