Petri net-based specification, analysis and synthesis of logic controllers

Węgrzyn, Agnieszka; Węgrzyn, Marek

doi:10.1109/isie.2000.930479

Cited by 13 publications

(7 citation statements)

References 7 publications

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“…The formal description of the PLC program can be either some highlevel functional representation or just a list of instructions in a programming language. Papers using high-level functional representations are [5]- [8], which are based on Petri nets and equivalent formulations and [9], which uses Sequential Function Charts. On the other hand, papers that work with individual PLC instructions are [10]- [11] and [2].…”

Section: Background and Related Workmentioning

confidence: 99%

FPGA implementation of PLC programs using automated high-level synthesis tools

Economakos¹,

Economakos

2008

2008 IEEE International Symposium on Industrial Electronics

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Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is that it requires expertise in both industrial automation and FPGAs. In this paper we propose a fully automated design methodology for producing efficient FPGA implementations of PLC programs. The PLC programs can be prepared by automation experts using their familiar programming environments and the conversion to FPGA is done by automated high-level synthesis tools. The advantages of this approach are demonstrated on a number of standard industrial control applications.

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Section: Background and Related Workmentioning

confidence: 99%

FPGA implementation of PLC programs using automated high-level synthesis tools

Economakos¹,

Economakos

2008

2008 IEEE International Symposium on Industrial Electronics

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“…In addition, all the nonleaf nodes of the AND-OR tree are nodes which are called either AND-nodes or OR-nodes. They will be defined in Condition (5) and Condition (6).…”

Section: The Use Of the And-or Tree In Thismentioning

confidence: 99%

“…Ikeshita et al [4] studied the mapping relationship between the fundamental elements (i.e., steps, actions, and transitions) in a sequential flow chart (SFC) and the Boolean variables expressed in Verilog-HDL language. Adamski and Monteiro [5] and A. Wegrzyn and M. Wegrzyn [6] discussed the interpretational relationship from Petri-net-based specifications to Boolean expressions in VHDL, but both studies have not proposed a conversion algorithm. Ichikawa et al [7] summarized the three kinds of operational modes of a PLC process when it is executed by the logic circuits inside the FPGA module.…”

Section: Introductionmentioning

confidence: 99%

An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams

Xie

Zhuang

2015

Mathematical Problems in Engineering

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This study proposes an algorithm for generating the associated Boolean expression in VHDL, given a ladder diagram (LD) as the input. The purpose of the algorithm is to implement of field-programmable gate array-(FPGA-) based programmable logic controllers (PLCs), where an effective conversion from an LD to its associated Boolean expressions seems rarely mentioned. Based on this core thought, the conversion process of the algorithm first involves abstracting and expressing the encountered LD as an activity-on-vertex (AOV) graph. Next, an AND-OR tree in which AND-nodes and OR-nodes connote the series and the parallel relationships between the vertices of the AOV graph is constructed based on the AOV graph. Therefore, by a traversal to the AND-OR tree, the associated Boolean expression, as the output of the algorithm, can be easily obtained in VHDL. The proposed algorithm is then verified with an illustrative example, wherein a complicated LD is given as the input.

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“…For example, Adamski and Monteiro [4,5] presented a design methodology that translates ‘interpreted Petri net specification’ into hardware description languages. Wegrzyn et al [6,7] presented a framework that transforms rule‐based descriptions (e.g., interpreted Petri net) into logic descriptions (e.g., VHDL). Ikeshita et al [8] presented a conversion program that translates sequential function chart (SFC) description into Verilog‐HDL for logic synthesis.…”

Section: Background and Related Studiesmentioning

confidence: 99%

An FPGA implementation of hard‐wired sequence control system based on PLC software

Ichikawa

Akinaka

Hata

et al. 2011

IEEJ Transactions Elec Engng

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Although a programmable logic controller (PLC) has been widely adopted for the sequence control of industrial machinery, its performance does not always satisfy the recent requirements in large and highly responsive systems. With the state‐of‐the‐art field programmable gate array (FPGA) technology, it is possible to implement a control program with hard‐wired logic for higher response and reduced implementation cost/space. This approach is also worthwhile for transmigration of legacy PLC software into forthcoming FPGA‐based control hardware. This study presents a systematic method to implement a hard‐wired sequence control from PLC software. PLC instructions are converted into VHDL codes, and then implemented as logic circuit with various peripheral functions. Productive PLC programs were examined with Mitsubishi Electric FX2N PLC and Altera Stratix II FPGA, and were shown to fit into a common FPGA chip. A straightforward Sequential design was estimated to be 184 times faster than PLC, while a performance‐oriented Flat design was estimated to be 44 times faster than Sequential design (i.e., 8050 times faster than PLC). A practical perfect layer winder system was actually built and successfully operated with our FPGA control board, whose logic design was implemented with our tools. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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Petri net-based specification, analysis and synthesis of logic controllers

Cited by 13 publications

References 7 publications

FPGA implementation of PLC programs using automated high-level synthesis tools

FPGA implementation of PLC programs using automated high-level synthesis tools

An Algorithm for Generating Boolean Expressions in VHDL Based on Ladder Diagrams

An FPGA implementation of hard‐wired sequence control system based on PLC software

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