Persistent hybrid transactional memory for databases

Abstract

Processors with hardware support for transactional memory (HTM) are rapidly becoming commonplace, and processor manufacturers are currently working on implementing support for upcoming non-volatile memory (NVM) technologies. The combination of HTM and NVM promises to be a natural choice for in-memory database synchronization. However, limitations on the size of hardware transactions and the lack of progress guarantees by modern HTM implementations prevent some applications from obtaining the full benefit of hardware transactional memory. In this paper, we propose a persistent hybrid TM algorithm called PHyTM for systems that support NVM and HTM. PHyTM allows hardware assisted ACID transactions to execute concurrently with pure software transactions, which allows applications to gain the benefit of persistent HTM while simultaneously accommodating unbounded transactions (with a high degree of concurrency). Experimental simulations demonstrate that PHyTM is fast and scalable for realistic workloads.

Hardware transactional persistent memory

“…Solutions like using an atomic counter within transactions to order them correctly are not practical since the shared counter will result in HTM-induced aborts and serialization of all transactions. Some papers have advocated that processor manufacturers alter HTM semantics and implementation to allow selective writes to PM from within an HTM [13,21,22]. We describe our solution without the need for such intrusive processor changes in Section 3.…”

“…Recent work [13,21,22] aims to exploit processor-supported HTM mechanisms for concurrency control instead of traditional locking or STM-based approaches. However, all of these solutions require making signi cant changes to the existing HTM semantics and implementations.…”

“…However, all of these solutions require making signi cant changes to the existing HTM semantics and implementations. For instance, PHTM [21] and PHyTM [22], propose a new instruction called TransparentFlush which can be used to ush a cache line from within a transaction to persistent memory without causing any transaction to abort. ey also propose a change to the xend instruction that ends an atomic HTM region, so that it atomically updates a bit in persistent memory as part of its execution.…”

“…For these, PTM [20] proposes changes to processor caches while adding an on-chip scoreboard and global transaction id register to couple HTM with PM. Recent work [13,21,22] has a empted to provide inter-transactional isolation by employing processor based (HTM) [7,8] mechanisms. However, these solutions all require changes to the existing HTM semantics and implementations- [21] and [22] propose a new instruction to perform non-aborting cacheline ush from within an HTM, while [13] proposes allowing non-aborting concurrent access to designated memory variables within an HTM. Selective and incremental changes to the clean isolation semantics of HTM are not to be undertaken lightly; understanding their impact on global system correctness and performance typically requires long gestation periods before processor manufacturers will embrace them.…”

Brief Announcement

“…PTM [15] proposes changes to processor caches while adding an on-chip scoreboard and global transaction id register to couple HTM with SCM. Recent work [1,2,12] has a empted to provide inter-transactional isolation by employing processor based Hardware Transactional Memory (HTM) [9,13] mechanisms. However, these solutions all require changes to the existing HTM semantics and implementations.…”