2020 IEEE International Symposium on Circuits and Systems (ISCAS) 2020
DOI: 10.1109/iscas45731.2020.9180521
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Performing Stochastic Computation Deterministically

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Cited by 2 publications
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“…It can be deduced that the smallest possible latency for a stochastic multiplier design is equal to 2N clock cycles, because any design faster than that would not even be able to receive complete inputs. Unlike deterministic techniques in [4], in order to achieve this minimum latency, repetition of input streams is not needed.…”
Section: Latency and Variable Precisionmentioning
confidence: 99%
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“…It can be deduced that the smallest possible latency for a stochastic multiplier design is equal to 2N clock cycles, because any design faster than that would not even be able to receive complete inputs. Unlike deterministic techniques in [4], in order to achieve this minimum latency, repetition of input streams is not needed.…”
Section: Latency and Variable Precisionmentioning
confidence: 99%
“…The result at 2Nth clock cycle is the exact full‐precision product. Latency is reduced by order of 2N compared to all the sequences and techniques suggested in [4].…”
Section: Latency and Variable Precisionmentioning
confidence: 99%
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