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Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis 2019
DOI: 10.1145/3295500.3356217
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Performance optimality or reproducibility

Abstract: The era of extremely heterogeneous supercomputing brings with itself the devil of increased performance variation and reduced reproducibility. There is a lack of understanding in the HPC community on how the simultaneous consideration of network traffic, power limits, concurrency tuning, and interference from other jobs impacts application performance. In this paper, we design a methodology that allows both HPC users and system administrators to understand the trade-off space between optimal and reproducible p… Show more

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Cited by 21 publications
(6 citation statements)
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“…Comparing several performance profiles is of significant interest to application developers aiming to identify performance bugs across versions of a code or to understand how different application parameters and/or initial conditions may affect the performance [12,45]. HPC experts are also interested in evaluating ensembles of performance profiles to assess the role of architecture choices, machine environments, MPI configurations, etc., to identify optimal execution and deployment modes [9,54].…”
Section: Domain Problem Characterizationmentioning
confidence: 99%
“…Comparing several performance profiles is of significant interest to application developers aiming to identify performance bugs across versions of a code or to understand how different application parameters and/or initial conditions may affect the performance [12,45]. HPC experts are also interested in evaluating ensembles of performance profiles to assess the role of architecture choices, machine environments, MPI configurations, etc., to identify optimal execution and deployment modes [9,54].…”
Section: Domain Problem Characterizationmentioning
confidence: 99%
“…Other system constraints such as I/O interference [12] or including consideration of network traffic, power limits or concurrency tuning in the HPC middleware [41], can also become a significant reason for performance variability. Although we could include them in our model, we chose to focus on application-specific variations, a new trend in HPC, and separate their impact from the hardware constraints.…”
Section: Related Workmentioning
confidence: 99%
“…Performance variability due to interference is highly evident as it may arise from on-chip variations [17,21], network activity [18,24], I/O traffic [12,13], etc. To study performance variability, Ates et al [3] introduce a performance anomaly generator for the major HPC subsystems that assesses the performance resilience of applications to different variability sources.…”
Section: Related Workmentioning
confidence: 99%
“…In these scenarios, common strategies to reduce interference include eliminating unnecessary activities such as process scheduling or memory management [23], and carefully managing interrupts to minimize application perturbation [27]. As the scale and heterogeneity of systems keeps increasing, tackling interference becomes an even larger concern [24]. While the aforementioned techniques can generally mitigate interference, sources of performance variability are overall very diverse in modern highly interconnected systems, and can only be addressed effectively in cooperation with application knowledge.…”
Section: Introductionmentioning
confidence: 99%