Performance optimal speed control of multi-core processors under thermal constraints

Hanumaiah,; Vrudhula,; Chatha,

doi:10.1109/date.2009.5090908

Cited by 10 publications

(6 citation statements)

References 9 publications

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“…Some recent works have developed temperature-control techniques for regular [Rohou and Smith 1999] and real-time [Bansal et al 2004;Bansal and Pruhs 2005;Wang and Bettati 2006b;Wang and Bettati 2006a;Hanumaiah et al 2009] workloads. The main approach is to dynamically adjust the CPU speed to minimize the peak temperature of the CPU, subject to the constraint that all jobs finish by their deadlines or as early as possible.…”

Section: Prior Workmentioning

confidence: 99%

Performance-aware thermal management via task scheduling

Zhou

Yang

Chrobák

et al. 2010

ACM Trans. Archit. Code Optim.

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High on-chip temperature impairs the processor's reliability and reduces its lifetime. Hardwarelevel dynamic thermal management (DTM) techniques can effectively constrain the chip temperature, but degrades the performance. We propose an OS-level technique that performs thermalaware job scheduling to reduce DTMs. The algorithm is based on the observation that hot and cool jobs executed in a different order can make a difference in resulting temperature. Real-system implementation in Linux shows that our scheduler can remove 10.5% to 73.6% of the hardware DTMs in a medium thermal environment. The CPU throughput is improved by up to 7.6% (4.1%, on average) in a severe thermal environment.

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Section: Prior Workmentioning

confidence: 99%

Performance-aware thermal management via task scheduling

Zhou

Yang

Chrobák

et al. 2010

ACM Trans. Archit. Code Optim.

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“…The phenomenon of high power density causes high temperature and cannot be ignored even under present technology [13] [19].…”

Section: Introductionmentioning

confidence: 99%

“…First, the packaging and cooling cost increases with increase in temperature [13]. Second, high temperature leads to the decrease of the carr ier mobility and the increase of interconnect resistivity, in turn causing the system performance to decrease [11].…”

Section: Introductionmentioning

confidence: 99%

Thermal analysis experiences of a tri-core SoC system

Lung

Huang

et al. 2010

The 2010 International Conference on Green Circuits and Systems

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Higher temperature induced by higher power density results in higher cost, lower performance and lower reliability.The thermal effects become important issues of today's VLSI design. In this paper, we adopt a RC-based thermal model to perform the steady-state and transient thermal analysis for a tri core SoC system. The power information is generated from the ESL power estimation. The results show that the lateral heat dissipation cannot be ignored since hot spots occur in the vicinity where the nearby blocks with high power density, but none of hot spots with the highest power density. Finally, we also compare our fast RC based thermal analysis model with commercial CFD (Computational Fluid Dynamics) software whose runtime is extremely slow. The results show the high degree of consistency.

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“…A number of modern microprocessors such as Intel's XScale [13], Transmeta's Cruso [14], AMD's Quad-core Opteron processor [15], and IBM's Power6 microprocessor [16], are equipped with DVFS functionality. Many algorithms have been proposed recently that use power and thermal-aware DVFS for single-and multi-core processors and have demonstrated their ability to reduce power consumption [17,18,19,20,21,22].…”

Section: Introductionmentioning

confidence: 99%

Modeling the effects of DFS on power consumption in hybrid chip multiprocessors

Marowka

2013

Proceedings of the 1st International Workshop on Energy Efficient Supercomputing

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The power wall is one of the primary stumbling blocks that many-core microprocessor architecture is facing today. To avoid this problem, microprocessor makers are shifting towards heterogeneous chips that integrate different core architectures on a single die and that have proved to deliver better performance per watt. Moreover, these new hybrid microprocessors are equipped with dynamic frequencyscaling techniques that are capable of reducing total system power consumption.This paper presents a theoretical study on how performance and power consumption are affected by the dynamic frequency-scaling techniques offered by the power constraints imposed on state-of-the-art dual-architecture processors. Analytical schemes have been developed to extend Amdahl's Law by accounting for energy limitations before examining the three processing schemes available to heterogeneous processors: symmetric, asymmetric, and simultaneous asymmetric. Analysis shows that by choosing the optimal chip configuration, power efficiency and energy savings can be increased considerably while keeping sacrifices in performance at tolerable levels.

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Performance optimal speed control of multi-core processors under thermal constraints

Cited by 10 publications

References 9 publications

Performance-aware thermal management via task scheduling

Performance-aware thermal management via task scheduling

Thermal analysis experiences of a tri-core SoC system

Modeling the effects of DFS on power consumption in hybrid chip multiprocessors

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